Date Index for si-list, 07-2001

[si-list] || [07-2001 Date Index] [07-2001 Thread Index]

[SI-LIST] Re: Validation of XTK results for clock skews - Suchitha . V
[SI-LIST] ADDITIONAL PCI CLOCKS - Chandan
[SI-LIST] High performance materials - Chris Mesibov
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - Robert_Washburn
[SI-LIST] Which computing platform for (Ansoft/Pacific Numerix) TPA - grhare
[SI-LIST] Re: Decoupling - Larry Smith
[SI-LIST] Re: Decoupling - Bob Weber
[SI-LIST] Re: Validation of XTK results for clock skews - abe riazi
[SI-LIST] FR4 - Rich Peyton
[SI-LIST] Re: High performance materials - Chris Robertson
[SI-LIST] Re: decoupling - Doug Brooks
[SI-LIST] Re: decoupling - Greim, Michael
[SI-LIST] si-list hardware failure on 7/7 thru 7/9 - Ray Anderson
[SI-LIST] Re: Which computing platform for (Ansoft/Pacific Numerix) TPA - Scott McMorrow
[SI-LIST] Re: FR4 - Martyn Gaudion
[SI-LIST] Re: FR4 - Greim, Michael
[SI-LIST] Re: FR4 - Seol Byongsu
[SI-LIST] Temperature vs. performance in different type of processes. - =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
[SI-LIST] Re: FR4 - Rich Peyton
[SI-LIST] stats si-list - marko . pulli
[SI-LIST] Re: decoupling - Khalid Ansari
[SI-LIST] Re: Temperature vs. performance in different type of processes. - Dagostino, Tom
[SI-LIST] Re: decoupling - Larry Miller
[SI-LIST] Re: power plane spacing - S. Weir
[SI-LIST] post layout SI analysis - Andrew H.Barr
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - Beal, Weston
[SI-LIST] Re: FR4 - Ritchey Lee
[SI-LIST] Board to Board connetcions using Coax cables - Sreejith Varma
[SI-LIST] Re: power plane spacing - Ritchey Lee
[SI-LIST] Re: Board to Board connetcions using Coax cables - Doug White
[SI-LIST] Re: decoupling - Ritchey Lee
[SI-LIST] Re: decoupling - Larry Smith
[SI-LIST] Re: decoupling - Chan, Michael
[SI-LIST] Re: FR4 - e_montgomery
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - Volk, Andrew M
[SI-LIST] Re: post layout SI analysis - Beal, Weston
[SI-LIST] Re: power plane spacing - Gonzo
[SI-LIST] Re: post layout SI analysis - May, John
[SI-LIST] Re: power plane spacing - Chris Padilla
[SI-LIST] Re: FR4 - Moran, Brian P
[SI-LIST] Re: power plane spacing - Ye, Xiaoning
[SI-LIST] Re: decoupling - S. Weir
[SI-LIST] Re: decoupling - Ed Priest
[SI-LIST] Re: decoupling - S. Weir
[SI-LIST] Re: decoupling - e
[SI-LIST] Re: decoupling - S. Weir
[SI-LIST] Re: power plane spacing - e
[SI-LIST] Re: decoupling - e
[SI-LIST] Re: power plane spacing - S. Weir
[SI-LIST] Re: power plane spacing - e
[SI-LIST] Re: power plane spacing - S. Weir
[SI-LIST] Re: post layout SI analysis - Tom Barber
[SI-LIST] Re: decoupling - Ken Cantrell
[SI-LIST] Re: post layout SI analysis - Ken Cantrell
[SI-LIST] Re: decoupling - Vinu Arumugham
[SI-LIST] Re: Board to Board connetcions using Coax cables - Sreejith Varma
[SI-LIST] Re: decoupling - Ed Priest
[SI-LIST] Re: power plane spacing - Bernard Voss
[SI-LIST] Re: decoupling - S. Weir
[SI-LIST] Re: decoupling - Mark Alexander
[SI-LIST] Re: decoupling - Ray Anderson
[SI-LIST] Re: decoupling - Khalid Ansari
[SI-LIST] Re: decoupling - Ray Anderson
[SI-LIST] Re: decoupling - Zhineng Fan
[SI-LIST] Re: decoupling - Ken Cantrell
[SI-LIST] Re: decoupling - Ken Cantrell
[SI-LIST] Re: decoupling - Ray Anderson
[SI-LIST] Re: decoupling - Chris Cheng
[SI-LIST] Re: decoupling - Vinu Arumugham
[SI-LIST] Re: post layout SI analysis - Juliusz Poltz
[SI-LIST] Re: decoupling - Ken Beach
[SI-LIST] Re: decoupling - S. Weir
[SI-LIST] Re: decoupling - Vinu Arumugham
[SI-LIST] Re: post layout SI analysis - Ken Cantrell
[SI-LIST] Re: decoupling - Ken Cantrell
[SI-LIST] Re: decoupling - Grossman, Brett
[SI-LIST] Re: post layout SI analysis - Teo Yatman
[SI-LIST] Primary Signal Integrity Hardware Tools - EADS,RICK (A-ColSprings,ex1)
[SI-LIST] Re: Primary Signal Integrity Hardware Tools - Zabinski, Patrick J.
[SI-LIST] Re: post layout SI analysis - zanella, fabrizio
[SI-LIST] extraction of RLGC matrices from Sigexplorer - Peter LaFlamme
[SI-LIST] Re: Primary Signal Integrity Hardware Tools - Bill Owsley
[SI-LIST] Re: extraction of RLGC matrices from Sigexplorer - Mike LaBonte
[SI-LIST] Re: extraction of RLGC matrices from Sigexplorer - ruston, matt
[SI-LIST] Re: extraction of RLGC matrices from Sigexplorer - dkhatri
[SI-LIST] Re: post layout SI analysis - Ken Cantrell
[SI-LIST] Re: Primary Signal Integrity Hardware Tools - Ken Cantrell
[SI-LIST] Re: post layout SI analysis - Ken Cantrell
[SI-LIST] Re: post layout SI analysis - Ken Cantrell
[SI-LIST] Re: Primary Signal Integrity Hardware Tools - Ken Cantrell
[SI-LIST] On-chip Terminations - Patrick Francq
[SI-LIST] Re: On-chip Terminations - Michael Nudelman
[SI-LIST] Re: On-chip Terminations - Zabinski, Patrick J.
[SI-LIST] Re: On-chip Terminations - Chuck Hill
[SI-LIST] IC Receiver Design for Low Jitter - Chuck Hill
[SI-LIST] Re: On-chip Terminations - ruston, matt
[SI-LIST] Re: post layout SI analysis - Richard A. Schumacher
[SI-LIST] Re: On-chip Terminations - D. C. Sessions
[SI-LIST] Re: post layout SI analysis - Scott McMorrow
[SI-LIST] Re: IC Receiver Design for Low Jitter - D. C. Sessions
[SI-LIST] Re: IC Receiver Design for Low Jitter - ABOULHOUDA,SAMIR (A-England,ex1)
[SI-LIST] Looking for Oztek and special SMA's - Dennis Rehm
[SI-LIST] Re: post layout SI analysis - Ken Cantrell
[SI-LIST] Re: Looking for Oztek and special SMA's - Dean Gonzales
[SI-LIST] Re: Looking for Oztek and special SMA's - Douglas S. Johnson
[SI-LIST] Re: IC Receiver Design for Low Jitter - jim freeman
[SI-LIST] Re: Looking for Oztek and special SMA's - Jerry Chow - 7192
[SI-LIST] Re: post layout SI analysis - Andrew H.Barr
[SI-LIST] Signal Integrity Position - ASIC : Cisco Systems, Inc. San Jose, CA - Zhiping Yang
[SI-LIST] Re: On-chip Terminations - Mark Alexander
[SI-LIST] Re: On-chip Terminations - Jerry Chow - 7192
[SI-LIST] Re: extraction of RLGC matrices from Sigexplorer - Todd Westerhoff
[SI-LIST] Re: On-chip Terminations - Patrick Francq
[SI-LIST] Re: On-chip Terminations - Mark Alexander
[SI-LIST] Re: On-chip Terminations - ruston, matt
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - Ingraham, Andrew
[SI-LIST] Re: On-chip Terminations - Mark Alexander
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - Paglia, Frank M
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - S. Weir
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - Moran, Brian P
[SI-LIST] Re: Temperature vs. performance in different type of processes. - Ingraham, Andrew
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - S. Weir
[SI-LIST] Re: Temperature vs. performance in different type of processes. - Volk, Andrew M
[SI-LIST] Re: decoupling - Larry Smith
[SI-LIST] Re: ADDITIONAL PCI CLOCKS - Moran, Brian P
[SI-LIST] Re: IC Receiver Design for Low Jitter - D. C. Sessions
[SI-LIST] Re: IC Receiver Design for Low Jitter - D. C. Sessions
[SI-LIST] Re: Looking for Oztek and special SMA's - Walter Kreiger
[SI-LIST] In EBD model? - Inmyung Song
[SI-LIST] Re: In EBD model? - =?big5?b?u6+kaLPHXChTLiBDLiBDaGFvXCk=?=
[SI-LIST] Re: In EBD model? - =?big5?b?u6+kaLPHXChTLiBDLiBDaGFvXCk=?=
[SI-LIST] Production testing of loaded PCB's power supply impedance - Peter Baxter
[SI-LIST] Re: Production testing of loaded PCB's power supply impedance - Greim, Michael
[SI-LIST] Re: In EBD model? - Beal, Weston
[SI-LIST] Injecting noise into a plane - Alokby, Ahmed
[SI-LIST] Re: Injecting noise into a plane - Khalid Ansari
[SI-LIST] SMT headers vs. SMA - Khalid Ansari
[SI-LIST] Re: Injecting noise into a plane - Dagostino, Tom
[SI-LIST] Re: Injecting noise into a plane - WEBB,JEREMY (A-Sonoma,ex1)
[SI-LIST] Re: Injecting noise into a plane - signal hoss
[SI-LIST] Re: On-chip Terminations - Jon Keeble
[SI-LIST] Buried resister in High Speed Digital Design? - Inmyung Song
[SI-LIST] Clock skew measurement using XTK simulation tool - Goutham . S
[SI-LIST] IBIS model - Goutham . S
[SI-LIST] Oscilloscope for POST SI Analysis - Adam Klein
[SI-LIST] Re: Clock skew measurement using XTK simulation tool - Jeremy Plunkett
[SI-LIST] High Speed Inter-board connections - Ron Kane
[SI-LIST] Re: decoupling - Zhiping Yang
[SI-LIST] Re: decoupling - S. Weir
[SI-LIST] Controlled impedance PCB question - Allan Davidson
[SI-LIST] Re: Controlled impedance PCB question - C Deibele
[SI-LIST] Question about package models - Allan Davidson
[SI-LIST] Re: Controlled impedance PCB question - Zabinski, Patrick J.
[SI-LIST] Re: Question about package models - Zabinski, Patrick J.
[SI-LIST] Re: Controlled impedance PCB question - Moran, Brian P
[SI-LIST] Re: Question about package models - Ozgur Misman
[SI-LIST] Re: Question about package models - Dagostino, Tom
[SI-LIST] Flash memory - Seol Byongsu
[SI-LIST] Mictor probes and 'high' speed/sensitive signals - S Tatlow
[SI-LIST] Re: decoupling - Wang Xiao-yun
[SI-LIST] Re: Controlled impedance PCB question - Dave Hoover
[SI-LIST] tools for assembly cost and metrics of printed circuit boards - jan . vercammen . jv1
[SI-LIST] set si-list vacation - Ilkka Lehikoinen
[SI-LIST] Re: decoupling - Zhiping Yang
[SI-LIST] Re: tools for assembly cost and metrics of printed circuit boards - James Freeman
[SI-LIST] Re: decoupling - Zhiping Yang
[SI-LIST] Re: decoupling - sweir
[SI-LIST] Re: post layout SI analysis - Mary
[SI-LIST] System Designers w/ SI skills needed in Santa Clara, CA - Mark Apton
[SI-LIST] Last Day in Force - Senthil . Selvam
[SI-LIST] Buried Resister in High speed digital design? - Inmyung Song
[SI-LIST] PCB material with er=2.5? - David Instone
[SI-LIST] LICA in flip chip BGAs - Yuan Li
[SI-LIST] Re: Question about package models - Chris Rokusek
[SI-LIST] ac drive strength - Peterson, James F (FL51)
[SI-LIST] need some help - Michael Allen
[SI-LIST] Re: ac drive strength - Chuck Hill
[SI-LIST] Re: need some help - Kai Keskinen
[SI-LIST] Re: need some help - Michael Allen
[SI-LIST] Re: Question about package models - Dagostino, Tom
[SI-LIST] Re: ac drive strength - D. C. Sessions
[SI-LIST] Transmission line simulation at 1.25GHZ - Ashok Babu K
[SI-LIST] AGP model - =?big5?b?Um9nZXIuV3UgKKdkrVqqTCk=?=
[SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION - Kai, Francis
[SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION - Kai, Francis
[SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION - Charles Grasso
[SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION - Ray Anderson
[SI-LIST] Re: SpecctraQuest - Todd Westerhoff
[SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION - Charles Grasso
[SI-LIST] Re: HOT SIGNAL INTEGRITY ENGINEER POSITION - Greim, Michael
[SI-LIST] Re: Transmission line simulation at 1.25GHZ - Rob Hinz
[SI-LIST] test message - Ignore and Delete - Ray Anderson
[SI-LIST] Re: SpecctraQuest - Carlos Moll
[SI-LIST] diff pair questions - signal hoss
[SI-LIST] Tool Recommendations? - Dennis Schmitz
[SI-LIST] Re: Tool Recommendations? - Teo Yatman
[SI-LIST] si-list administrivia - Ray Anderson
[SI-LIST] Re: si-list administrivia - Beal, Weston
[SI-LIST] Re: si-list administrivia - Geoff Haines
[SI-LIST] Re: si-list administrivia - Geoff Haines
[SI-LIST] Re: diff pair questions - Chris Rokusek
[SI-LIST] Re: si-list administrivia - S. Weir
[SI-LIST] Re: diff pair questions - signal hoss
[SI-LIST] AMD Forms Hyper-Transport I/O Consortium - Jonathan Dowling
[SI-LIST] Re: diff pair questions - Chris Rokusek
[SI-LIST] Re: diff pair questions - Daniel, Erik S.
[SI-LIST] Re: si-list administrivia - Rich Peyton
[SI-LIST] Re: Tool Recommendations? - Javin Olson
[SI-LIST] IBIS Model for Multi-Chip Package - Aaron Frank
[SI-LIST] Re: IBIS Model for Multi-Chip Package - Peters, Stephen
[SI-LIST] Re: diff pair questions - Vinu Arumugham
[SI-LIST] Results of the "Reply To:" survey - Option B wins - Ray Anderson
[SI-LIST] EMI and Power plane card edge clearance distance - Stacy L Gore
[SI-LIST] Re: diff pair questions - signal hoss
[SI-LIST] Re: diff pair questions - signal hoss
[SI-LIST] Re: EMI and Power plane card edge clearance distance - David Heald
[SI-LIST] Re: diff pair questions - Vinu Arumugham
[SI-LIST] Re: Results of the "Reply To:" survey - Option B wins - EMCCOMPLY
[SI-LIST] Re: EMI and Power plane card edge clearance distance - winson yu
[SI-LIST] Re: diff pair questions - Daniel, Erik S.
[SI-LIST] LVDS Glitch Problem - Denomme, Paul S.
[SI-LIST] Re: Tool Recommendations? - Doug Hopperstad
[SI-LIST] Re: LVDS Glitch Problem - S. Weir
[SI-LIST] Re: LVDS Glitch Problem - S. Weir
[SI-LIST] Re: IBIS Model for Multi-Chip Package - Dagostino, Tom
[SI-LIST] Re: IBIS Model for Multi-Chip Package - Scott McMorrow
[SI-LIST] Re: ac drive strength - Muranyi, Arpad
[SI-LIST] Re: ac drive strength - Greim, Michael
[SI-LIST] Re: Tool Recommendations? - Todd Westerhoff
[SI-LIST] Re: ac drive strength - Beal, Weston
[SI-LIST] HSPICE to print HEX question - dan hariton
[SI-LIST] Re: si-list administrivia - David Instone
[SI-LIST] Re: si-list administrivia - Ken Cantrell
[SI-LIST] Re: AMD Forms Hyper-Transport I/O Consortium - Ken Cantrell
[SI-LIST] IBIS and device performance - Todd Westerhoff
[SI-LIST] Creating IBIS Electrical Board Descriptions - Aaron Frank
[SI-LIST] Rise time calculation - Jinto N.Jose
[SI-LIST] Re: ac drive strength - Chuck Hill
[SI-LIST] Re: Tool Recommendations? - Donald Telian
[SI-LIST] differential trace mismatch - Mellberg Hans
[SI-LIST] Alloy-42 ur and sigma ... - Neeraj Pendse
[SI-LIST] Re: Alloy-42 ur and sigma ... - Rich Peyton
[SI-LIST] PCI Bus Ringing, Overshoot - Simba Julian
[SI-LIST] Placement of decoupling capacitors - Khalid Ansari
[SI-LIST] Fiber Channel simulation - =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
[SI-LIST] Re: Rise time calculation - subramanya C K
[SI-LIST] Re: PCI Bus Ringing, Overshoot - subramanya C K
[SI-LIST] Re: Rise time calculation - Ravikumar Chirugudu
[SI-LIST] Re: differential trace mismatch - Martin.J Thompson
[SI-LIST] Design with DDR (SSTL-2) memory - Ravinder Ajmani
[SI-LIST] Re: differential trace mismatch - Doug Brooks
[SI-LIST] Re: Placement of decoupling capacitors - Khalid Ansari
[SI-LIST] Vp on serpentine - Mellberg Hans
[SI-LIST] Re: Placement of decoupling capacitors - Ray Anderson
[SI-LIST] Re: Placement of decoupling capacitors - Khalid Ansari
[SI-LIST] Re: Placement of decoupling capacitors - Ray Anderson
[SI-LIST] Re: Placement of decoupling capacitors - S. Weir