FreeLists / si-list / [SI-LIST] HW DIRECTOR CISCO SYSTEMS IMMEDIATE OPENING

["Catherine Paradiso -X \(caparadi - Spherion at Cisco\)" <caparadi@xxxxxxxxx>]

Content-Type: text/plain;
        charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
HW DIRECTOR

An opportunity to own the SI piece of Cisco's Next Generation Products,
5.5 billion dollar BU.

=20

IMMEDIATE OPENING! Must be authorized to work in the US and available
ASAP!

=20

Looking for:

2 years SI management experience, with the ability to build your own
team.=20

=20

At least 10 years of design experience in timing, verification,
analysis, signal

integrity, flow and methodology..

=20

Technical Skills

Spice, Verilog, IBIS, C++, Java, C, shell script, Perl, timing,
modeling, simulation, verification, signal integrity, Hspice, Allegro
SI, Concepthdl, Primetime, ADS, CSTCircuit (Hspice) TL, CML, LBDS,
Electromagnetics, Materials (electrical aspect) Measurements

=20

Technical Exposure

=20




Signal integrity related development for company's advanced enterprise
Gigabit

Ethernet switches. SI related design, modeling and analysis on Serdes,
QDR,

DDR, package, interconnect and board layout. Work with ASIC vendors and
off

the shell chip suppliers to ensure good SI design, methodology and
integration inthe hardware system development.

=20

Signal integrity related development for company's advanced high speed
I/O and package technology. Architect and lead the design and
implementation of IO SI=20

=20

Design Kits for customers' ASIC development to maximize customers'

satisfaction and first pass success. Developed system layout guidelines
for DDR, QDR and LVDS interfaces and reference test board.

=20

Design and analysis of SI related development on de-coupling, power

distribution, IR drop for enterprise/main frame data center servers. SI
design and cross talk analysis on midrange server systems. Managed and
provided

simulation environment for high speed system design.=20

Established and maintained constraint driven flow, signal integrity
methodology and design process.=20

=20

Evaluated new high speed EDA tools and worked with vendors to resolve
critical bugs and design issues.

=20

Worked with processor and ASIC teams on timing verification with
Primetime,

PrimetimeSI and Pearl static timing tools. Developed scripts and Java
programs for verification.=20

=20

Timing analysis on chipsets such as graphics, data-switch and Sparc
chips. Spice simulation on system I/O timing and constraints for buses
such as PCI and DDR.=20

=20

Managed and provided technical expertise for circuit

simulation and timing analysis toolsets such as Hspice, Primetime and
Pearl.

=20

Developed software to integrate various EDA tools, to establish a
coherent flow

and to speed up simulations. Taught SI and PCB design classes at Sun

University.

=20

=20

Developed floor planning and placement toolset for accurate placement of
macro

cells on to high speed GaAs gate arrays. Providing real-time design rule

checking, routing congestion analysis, region partitioning, cell-to-cell
wire delay

calculation, parasitic extraction and IR drop hotspot.=20

=20

Developed and maintained

design flow and toolkit for external customers on synthesis, simulation,

placement and routing. Assisted customers in simulation and cell
modeling.

=20

Developed software to translate 3rd party models and netlists into
internal

database system. Developed interface to Cadence's backend place and
route.

Mentor Graphics, Wilsonville, OR summer 1990

=20

Established design test cases for qualifying key simulators such as Lsim
before

production release. Developed new process and methodology for QA
release.

=20

Research and design of a hybrid digital/analog multiplier using
charge-couple

capacitors with CMOS technology for matrix solver with Hspice, Mentor
Graphics'

layout and simulation tools(Lsim).

=20

Designed and built hardware and software drivers to integrate computer,
digital voice synthesizer to the analog phone system with RS232
protocol, UART and firmware.=20

=20

Re-designed and re-wired the entire sound studio to maximize signal

quality and signal to noise ratio.




=20

=20

Does the shoe fit???..... Can you be available in a reasonable amount of
time?

Are you located or willing to locate in San Jose?

=20

If so, please email your resume to:  caparadi@xxxxxxxx

=20

Perhaps you are not interested, who do you know that may be interested
and has the appropriate skills and experience? Friend? Neighbor?
Colleague? Relative?  This is a great opportunity for a Senior HW Signal
Integrity Engineer!

Your help will be greatly appreciated!

=20

=20

=20

=20
=20
=20
Cathi Paradiso
SR Recruiter
Talent Acquisition and Management

caparadi@xxxxxxxxx
Phone :800-491-6705




United States
www.cisco.com <http://www.cisco.com/>=20

 =09
This e-mail may contain confidential and privileged material for the
sole use of the intended recipient. Any review, use, distribution or
disclosure by others is strictly prohibited. If you are not the intended
recipient (or authorized to receive for the recipient), please contact
the sender by reply e-mail and delete all copies of this message.=09
=20



-- Binary/unsupported file stripped by Ecartis --
-- Type: image/gif
-- File: logo.gif
-- Desc: logo.gif


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu