FreeLists / si-list / [SI-LIST] Re: matching within 1 mil

[Bill Wurst <billw@xxxxxxxxxxx>]

This has been an interesting topic, to say the least, including all of 
the threads that the original question spawned, this being one of them. 
  Most interesting is the wide diversity in perspectives offered, all 
valid.  Let me offer an historical perspective, and a frustration.

The first board I designed with a differential pair was laid out with 
tape on mylar (circa 1980) at 4:1 magnification.  No length matching was 
specified.  Basically, if each side of the pair looked symmetrical to 
the eye, it would work well given the state of ECL technology then. 
Length matching of data buses and data/clock signals typically wasn't a 
concern as the board delay skews were insignificant relative to IC 
specifications.

By the late 80's I was using CAD tools, and now we had the ability to 
"measure" trace lengths, precisely control width and space, and enter 
constraints.  Differential skews were specified at 100mils as it was 
easy for the layout designer and the resulting skew was a relatively 
small portion of the overall error budget.

Today, we now have some interfaces where 100mils is no longer adequate. 
  I know that because I take the time to go through the math, and will 
specify what I believe is appropriate given all of the other variations 
that can affect skew.  Here in lies the frustration:  more often than 
not, the layout designer will come back and say to me, "I know you only 
needed this matched to XXmils, but it was just as easy for me to match 
it to 1mil, so that's what I did."  Now, I have a hard time believing 
that it didn't involve a lot of extra work to get down to 1mil, but I'm 
not about to do his job for him nor do I wish to micro-manage him.  In 
all other respects, these folks are excellent at what they do, but this 
typical response makes me wonder why I went through the trouble of 
figuring out a more practical number in the first place.  Judging from 
the various responses, I'm not alone.  And I know that while the tool 
reports the lengths as matching to within 1mil, there may be as much as 
a few mils difference within the pad itself.  I know because I've sat 
down with designers and together we've discovered this.  (As an aside, 
it would be nice if CAD tools could report trace length minus the trace 
segments (or portions thereof) buried in pads.)

Mainly I'm venting and not looking for a response, but if anyone has had 
similar experiences and can think of constructive ways of "educating" 
layout designers, I'd like their opinions.

Regards,
     -Bill


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Stephen Zinck wrote:
> I echo this...
> 
> To my way of thinking, the first step should be understanding the interface 
> from a margin perspective. Length matching, trace spacing, stackup design, 
> layer usage (and the plethora of other tools we use - termination 
> methodology, topology, etc.) should be just that... tools a designer can 
> utilize to squeak ps of margin out of design, especially with high-speed 
> memory interface margins today being under 100ps. But if plenty of margin 
> exists, the length matching rules, etc. should be moderated to ease the 
> layout design, saving time and money. Science should have an important role 
> in the decision making process...
> 
> Steve
> 
> Stephen P. Zinck
> Interconnect Engineering Inc.
> P.O. Box 577
> South Berwick, ME 03908
> Phone - (207) 384-8280
> Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
> Web - www.interconnectengineering.com
> 
> 
> ----- Original Message ----- 
> From: "Kihong Kim" <joshuakh@xxxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Sent: Friday, June 01, 2007 11:43 AM
> Subject: [SI-LIST] Re: matching within 1 mil
> 
> 
> 
>>I agree on Jeff's view quite happily.
>>This is about the optimization among physical constraints including cost.
>>
>>Signal integrity is not pursuing THE best signal quality.
>>
>>I think it should pursue most optimal signal quality under the imposed
>>constraints.
>>
>>
>>Kihong Joshua Kim
>>
>>SI in Photonics and Electronics
>>
>>
>>
>>
>>>
>>>On 6/1/07, Loyer, Jeff <jeff.loyer@xxxxxxxxx > wrote:
>>>
>>>>I think folks are missing Bill's point.  I don't think he's saying that
>>>>the design is going to break at 2 mils routing difference, only that he
>>>>can easily attain a maximum 1 mil delta, so he uses that as his
>>>>constraint.  If his CAD folks balked at that number, he'd probably
>>>>adjust accordingly and, if it got close to having significant impact,
>>>>would do a more detailed analysis.
>>>>
>>>>This is very similar to what we've done for common-clock FSB signals:
>>>>tell our CAD folks to match them within 10 mils (or some number), even
>>>>though we know we can absorb more.  But, 10 mils is easily attainable,
>>>>and guarantees essentially no skew due to length differences.  Granted,
>>>>it's a little more work on CAD's part, but the tradeoff is I don't have
>>>>to do a grand analysis to figure out exactly how close they HAVE to be
>>>>matched, and then worry about whether my analysis was correct (and
>>>>require subsequent validation in the lab, etc.).=20
>>>>
>>>>This is about compromises, and where you put your energy into in-depth
>>>>analysis.  If you can easily do 1 mil spacing, no problem.  It's a
>>>>little tighter than I'd generally specify, but it's not absurd, either.
>>>>If you're using an auto-router (that's surprising to me, I didn't think
>>>>leading-edge designs could use them), you probably have different
>>>>constraints.
>>>>
>>>>Jeff Loyer
>>>>------------------------------------------------------------------
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