FreeLists / si-list / [SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion

[Bill Owsley <wdowsley@xxxxxxxxx>]

Chris,
  Have we met?  I don't usually invoke such a passionate response without a 
personal introduction.
Chris Cheng <Chris.Cheng@xxxxxxxx> wrote:
  "There is a considerable industry devoted to providing the various solutions 
to correcting all the manifestations of problems in SI and EMC. We wouldn't 
want to put them out of business now, would we?"

I other words, you don't even know why you need to do the things you say, you 
just want to justify your existence and your PCB designer wants to look busy 
meeting your pointless demand. Two wrong don't make one right.
No one articulate anything to justify what you said. You can't even do that 
yourself. First your want to dance around in SI, you realize you are going no 
where and you try to say "I am the EMI guy, SI deals with mV, I do uV"
Either show me an example or give us data.
________________________________

From: Bill Owsley [mailto:wdowsley@xxxxxxxxx]
Sent: Sat 6/2/2007 10:07 AM
To: Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Students - matching 1 mil IEEE1394/ethernet guidelines 
and DM to CM conversion


Exactly,
or in many more words... Warning! It's philosophical, not technical.
As so well articulated by so many on the list, that's not likely to be 
possible, as you intuitively sensed. And at what point could a fail be 
demonstrated? Would we then design to that point minus 1? or 2? or what number 
for a margin? Has any differential pair ever failed SI or EMC? What might have 
been done to correct the problem? I suggested a limit for only one aspect of 
the many possible solutions, which in my estimation, eliminates one of the many 
items to check. There are so many more. I work with guys that use tools that 
can do this with apparent ease - no problem. Others use what they have to do 
what they can - again, no problem. There is a considerable industry devoted to 
providing the various solutions to correcting all the manifestations of 
problems in SI and EMC. We wouldn't want to put them out of business now, would 
we?


Chris Cheng wrote:

In order words, you throw a lot of terms out and have no example.

-----Original Message-----
From: Bill Owsley [mailto:wdowsley@xxxxxxxxx]
Sent: Friday, June 01, 2007 5:56 PM
To: Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Students - matching 1 mil IEEE1394/ethernet guidelines 
and DM to CM conversion


Most systems are quite functional (SI) when presented to EMC for testing, and 
quite often fail. And as so many have very eloquently (where's my spell check) 
explained, there is not likely any 1 mil mis-match in a matched pair that 
caused it. So given my realm of influence, (which certainly is not the weave of 
FR4. Is there a felt or random pattern FR4?) I ask for continuous incremental 
improvements (that don't get me necktie party). I suspect that the weave 
variation of FR4 over any run of interest would have a plus and minus shift 
that on the average would come out near the nominal - remember odd/even number 
of twists for a pair, that odd number twist would unlock pandoras box. And 
certainly the other sources mentioned that are not the diff-pair trace length 
can be the dominate source of problem, but they were not part of the trace 
length constraint. 

Thanks to those that brought up the BER, RJ, any other jitter, eye diagrams and 
that stuff of SI world. All those numbers scare me in some fashion, they are so 
big.
And it seems that a better match in trace lengths given the phase percentage 
mentioned in another note and other descriptions of the effects, or lack of, 
for excessive constraints for differential signalling, that the little X mark 
in the middle of eye diagram seems to shrink, the supposed flat segments of the 
eye diagram are a little bit flatter. In a tightly couple pair, the forward 
crosstalk to the other signal of the pair is a little bit closer in phase with 
better matching and so does not cause as much of a slight shift in the 
crossover or switching point, leading to less jitter. Some of the multilevel 
signalling has such small differences in the discrete levels that any small 
improvement in the little effects that degrade these levels would seem to be 
better. Does a 1 mil request/constraint do that and at what cost? Well now, 
that all depends on where you would like to be in the market.




Chris Cheng wrote:

Show me a case where 1 mil difference will break SI.
Then.
Show me a case where 1 mil difference will break EMI but not SI.


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bill Owsley
Sent: Friday, June 01, 2007 2:29 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Students - matching 1 mil IEEE1394/ethernet
guidelines and DM to CM conversion


If any students are still with us, the ongoing interchange might indicate that 
these subjects are indeed interesting and can be somewhat complex in that there 
are a number of variable to keep in mind - all at once. 
And maybe enough information to get your project done well.
You're welcome... < > really stupid grin within the brackets

And this all started with a simple help me with my project question.

Since this is an SI list, the EMC aspects seem a little less important. I'm 
reminded of a class on how to use one of those CAD tools for schematic capture, 
layout, SI, EMC. The SI guys got to go home a day early since their concern in 
class was millivolts. The EMC guys had to stay over a day to work on the 
microvolts part.

And there is at least one layout group that has for me, a short rope and tall 
tree. But I love them anyway.

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