FreeLists / si-list / [SI-LIST] Re: Matching within 1 mil is just plain sillyness

[Scott McMorrow <scott@xxxxxxxxxxxxx>]

Jeff

It also depends on intra-pair vs. inter-pair(net) matching 
requirements.  Even 10 mils can be a royal PITA if you're trying to 
match a 64 bit bus that is fanned out.

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

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Teraspeed® is the registered service mark of
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Loyer, Jeff wrote:
> I think Ken and Jeff S. hit on the key here.  At what point do your CAD
> folks balk at a length matching spec?  In my experience, matching to
> within 10 mils is easily accomplished and I consider the possible 1.7ps
> skew electrically invisible (for the reasons Scott and many others
> cited).  So, 10 mils turns into my default length matching requirement,
> if one is required.
>
> In the presence of pushback from CAD on that number, I start doing more
> detailed analysis.  But, the feedback I have from my CAD folks (and I
> work with them very closely) is that, if they're going to have to match
> anyway, it's usually not a big difference to match to within 10mils
> instead of 100 (there are exceptions, and I deal with them on a
> case-by-case basis, usually relaxing the rule).  Jeff S. may have
> different tools or techniques that makes 100 mils his "pain threshold"
> number.
>
> It appeared to me that Bill's CAD folks were saying that 1 mil wasn't a
> problem, so that's the magic number he uses.
>
> Disclaimer:
> The content of this message is my personal opinion only and although I
> am an employee of Intel, the statements I make here in no way represent
> Intel's position on the issue, nor am I authorized to speak on behalf of
> Intel on this matter.
>
> Jeff Loyer
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Ken Cantrell
> Sent: Friday, June 01, 2007 12:46 PM
> To: jseeger@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Matching within 1 mil is just plain sillyness
>
> Jeff et al -
> Anytime I go under a 100 mils, my CAD guys want an explanation.  And
> they
> don't want theory.  I match lengths according to degrees of phase at the
> frequency of operation.  The max I go is 4 to 5 degrees of phase.  At
> 1GBs,
> one UI(bit width)is 1 nS.  For FR4, Er =3D 4.0, 1 deg =3D 33 mils.  3 =
> deg ~
> 100
> mils.  The maximum frequency for 100 mils matching would be ~ 875MHz.
> Anthing faster than that I would match at less than 100 mils.  I think
> this
> whole area is fertile ground for research, since it seems to be pretty
> arbitrary in the literature.
> Ken
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Jeff Seeger
> Sent: Friday, June 01, 2007 12:38 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Matching within 1 mil is just plain sillyness
>
>
>
> Thank you, Scott and Lee, for defending the physical designer.
>
> For decades now, we've been asked to meet rules like 1 mil, 10 mils,
> 100 mils. I often dig further and find we're working with 1 nS edges
> or skew budgets in 100s of pS.
>
> Unlike the machine shop, we can't laugh as the next guy will simply
> put the take-up wire length under the pad.
>
> And FWIW when arranging skew on a complex topology, what sounds like
> "free" on one path increases difficulty, layers, or both by orders
> of magnitude on wide busses or between large, densely arrayed parts.
>
> I find this "free" effort is usually coming out of my hide.  Maybe
> there are in-house groups where this effort is intentionally funded?
>
> --
>
>       Jeff Seeger                         Applied CAD Knowledge Inc
>       Chief Technical Officer                  Tyngsboro, MA  01879
>       jseeger "at" appliedcad "dot" com                978 649 9800
>
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