Date Index for si-list, 06-2007

[si-list] || [06-2007 Date Index] [06-2007 Thread Index]

[SI-LIST] JTAG - jeba singh
[SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines - Craig Twardy
[SI-LIST] matching within 1 mil - Loyer, Jeff
[SI-LIST] Re: matching within 1 mil - Kihong Kim
[SI-LIST] Re: matching within 1 mil - Bill Owsley
[SI-LIST] USB cable model - mukul pingley
[SI-LIST] Re: IEEE1394/Ethernet Routing Guidelines - Bill Owsley
[SI-LIST] Re: USB cable model - dmitry.a.smolyansky
[SI-LIST] Matching within 1 mil is just plain sillyness, IMO - Scott McMorrow
[SI-LIST] Re: matching within 1 mil - Stephen Zinck
[SI-LIST] Question about differental to common mode conversion - Allan Wang
[SI-LIST] Re: Question about differential to common mode conversi on - Clewell, Craig
[SI-LIST] Re: Matching within 1 mil is just plain sillyness - Jeff Seeger
[SI-LIST] Re: matching within 1 mil - Gisin, Franz
[SI-LIST] Re: Matching within 1 mil is just plain sillyness - Ken Cantrell
[SI-LIST] Re: Matching within 1 mil is just plain sillyness - Loyer, Jeff
[SI-LIST] Re: Matching within 1 mil is just plain sillyness - Scott McMorrow
[SI-LIST] Re: Matching within 1 mil is just plain sillyness - Jeff Seeger
[SI-LIST] Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Bill Owsley
[SI-LIST] Re: Matching within 1 mil is just plain sillyness - Jeff Seeger
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Chris Cheng
[SI-LIST] Re: Matching within 1 mil is just plain sillyness - Steve Barton
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Scott McMorrow
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Leonard Dieguez
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Bill Owsley
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Chris Cheng
[SI-LIST] JTAG-EJTAG - jeba singh
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Bill Owsley
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - steve weir
[SI-LIST] Re: Matching within 1 mil is just plain sillyness - Lee Ritchey
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Chris Cheng
[SI-LIST] Re: JTAG-EJTAG - PRAJIT S NAIR
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Bill Owsley
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - Bill Owsley
[SI-LIST] way off topic don't you think? - Bill Owsley
[SI-LIST] Re: Students - matching 1 mil IEEE1394/ethernet guidelines and DM to CM conversion - steve weir
[SI-LIST] Common design flaws that keep showing up in new designs - Doug Smith
[SI-LIST] Re: FER Test Vs BER Test in SATA - Charles Hill
[SI-LIST] Re: matching within 1 mil - Bill Wurst
[SI-LIST] Re: matching within 1 mil - Jack Olson
[SI-LIST] Re: matching within 1 mil - Scott McMorrow
[SI-LIST] Re: matching within 1 mil - jon_powell37
[SI-LIST] Re: matching within 1 mil - jon_powell37
[SI-LIST] Mil or Mils? - Chris Padilla \(cpad\)
[SI-LIST] Re: matching within 1 mil - steve weir
[SI-LIST] Re: matching within 1 mil - Jack Olson
[SI-LIST] Re: matching within 1 mil - Jack Olson
[SI-LIST] Re: matching within 1 mil - steve weir
[SI-LIST] Re: matching within 1 mil - steve weir
[SI-LIST] Re: matching within 1 mil - Scott McMorrow
[SI-LIST] Re: matching within 1 mil - Alan Hilton-Nickel
[SI-LIST] Re: Mil or Mils? - Richard Feldman
[SI-LIST] Re: matching within 1 mil - Scott McMorrow
[SI-LIST] Re: Mil or Mils? - Chris Padilla \(cpad\)
[SI-LIST] Re: matching within 1 mil - Salkow, Steven
[SI-LIST] Re: matching within 1 mil - Jack Olson
[SI-LIST] Flicker noise simulation - Vadim Heyfitch
[SI-LIST] Re: matching within 1 mil - Scott McMorrow
[SI-LIST] soldering plastic balls - david stern
[SI-LIST] Re: Mil or Mils? - Simon Aglionby
[SI-LIST] Re: soldering plastic balls - Lars Juul
[SI-LIST] Re: soldering plastic balls - steve weir
[SI-LIST] Re: soldering plastic balls - Lars Juul
[SI-LIST] Re: soldering plastic balls - Lars Juul
[SI-LIST] Re: soldering plastic balls - steve weir
[SI-LIST] Re: soldering plastic balls - steve weir
[SI-LIST] Re: soldering plastic balls - olaney
[SI-LIST] Re: soldering plastic balls - Moreira, Jose
[SI-LIST] Re: soldering plastic balls - steve weir
[SI-LIST] Re: soldering plastic balls - olaney
[SI-LIST] Re: soldering plastic balls - Scott McMorrow
[SI-LIST] Re: soldering plastic balls - Scott McMorrow
[SI-LIST] Re: soldering plastic balls - Lars Juul
[SI-LIST] Re: soldering plastic balls - Lee Ritchey
[SI-LIST] Re: soldering plastic balls - Scott McMorrow
[SI-LIST] HW DIRECTOR CISCO SYSTEMS IMMEDIATE OPENING - Catherine Paradiso -X \(caparadi - Spherion at Cisco\)
[SI-LIST] Asian IBIS Summit (China) First Announcement - Bob Ross
[SI-LIST] Re: USB cable model - ronald miller
[SI-LIST] Re: USB cable model - olaney
[SI-LIST] Join the thousands of people who got slim - Maryellen Stevenson
[SI-LIST] Power Plane - Split Plane - Jarbas Aryel Nunes da Silveira
[SI-LIST] Power Planes - 3.3V / 2.5 - Jarbas Aryel Nunes da Silveira
[SI-LIST] Re: Power Planes - 3.3V / 2.5 - tfox
[SI-LIST] Intel Intern Position Opened - Chinn, Gordon
[SI-LIST] Re: Power Planes - 3.3V / 2.5 - Terry Fox
[SI-LIST] Re: Question about differental to common mode conversion - tao xu
[SI-LIST] Getting started material for S-parameters for passive interconnect - Aubrey_Sparkman
[SI-LIST] Re: Getting started material for S-parameters for passive interconnect - Barnes, Heidi
[SI-LIST] Characteristic Impedance - sunil bharadwaz
[SI-LIST] Re: Getting started material for S-parameters for passive interconnect - Hill, John
[SI-LIST] Re: Characteristic Impedance - Lynne D. Green
[SI-LIST] Re: Characteristic Impedance - Joseph Kao
[SI-LIST] Re: Characteristic Impedance - Peterson, James F (EHCOE)
[SI-LIST] Silicon Image Signal Integrity Job Position Opened - Seungyong Baek
[SI-LIST] Diif pair geometry trade offs - Joel Brown
[SI-LIST] Principal Signal Integrity Engineer - Darrin Baja
[SI-LIST] Resistor package - model - OPREA Dorin
[SI-LIST] Re: Resistor package - model - Fabrizio . Zanella
[SI-LIST] Diif pair geometry trade offs - tfox
[SI-LIST] Anti-copper around BNC center conductor vs. return loss in HD input circuits. - tom_cip_11551
[SI-LIST] Re: Resistor package - model - OPREA Dorin
[SI-LIST] Re: Diif pair geometry trade offs - Ken Cantrell
[SI-LIST] Re: Diif pair geometry trade offs - Joel Brown
[SI-LIST] Re: Diif pair geometry trade offs - Bill Owsley
[SI-LIST] Re: Diif pair geometry trade offs - Muranyi, Arpad
[SI-LIST] Modeling conductor effects in serial data channel interconnects - Rick Yates
[SI-LIST] SSTL_2 doubt - Canes Venatici
[SI-LIST] Re: SSTL_2 doubt - Kihong Kim
[SI-LIST] Re: Diif pair geometry trade offs - Lee Ritchey
[SI-LIST] Re: Diif pair geometry trade offs - Vinu Arumugham
[SI-LIST] Re: Diif pair geometry trade offs - Vadim Heyfitch
[SI-LIST] Re: Diif pair geometry trade offs - Lee Ritchey
[SI-LIST] Re: Diif pair geometry trade offs - Lee Ritchey
[SI-LIST] Re: Diif pair geometry trade offs - Leonard Dieguez
[SI-LIST] Re: Diif pair geometry trade offs - Vinu Arumugham
[SI-LIST] Re: Diif pair geometry trade offs - Bill Owsley
[SI-LIST] HIGH DC Current on GND Plane - Joe Paul M
[SI-LIST] Re: HIGH DC Current on GND Plane - Doug Brooks
[SI-LIST] Re: Diif pair geometry trade offs - Powell, Jon N
[SI-LIST] Re: Diif pair geometry trade offs - Bill Owsley
[SI-LIST] Re: Anti-copper around BNC center conductor vs. return loss in HD input circuits. - steve weir
[SI-LIST] Re: Diif pair geometry trade offs - steve weir
[SI-LIST] Re: Diif pair geometry trade offs - Lee Ritchey
[SI-LIST] passive component .vs. series component - Kazuyuki Hagiwara
[SI-LIST] Re: SSTL_2 doubt - raj singh
[SI-LIST] Re: passive component .vs. series component - steve weir
[SI-LIST] Re: SSTL_2 doubt - steve weir
[SI-LIST] Re: Diif pair geometry trade offs - Loyer, Jeff
[SI-LIST] Re: passive component .vs. series component - Andrew Ingraham
[SI-LIST] Re: HIGH DC Current on GND Plane - Townsend, Fred
[SI-LIST] Re: passive component .vs. series component - Kazuyuki Hagiwara
[SI-LIST] Re: Diif pair geometry trade offs - Lee Ritchey
[SI-LIST] Re: Diif pair geometry trade offs - Joel Brown
[SI-LIST] Re: Diif pair geometry trade offs - Joel Brown
[SI-LIST] f vs. Tf vs. jitter - Steven Kan
[SI-LIST] Re: Diif pair geometry trade offs - Scott McMorrow
[SI-LIST] Re: Diif pair geometry trade offs - Scott McMorrow
[SI-LIST] Re: Diif pair geometry trade offs - steve weir
[SI-LIST] Re: passive component .vs. series component - Andrew Ingraham
[SI-LIST] Re: Diif pair geometry trade offs - steve weir
[SI-LIST] Re: f vs. Tf vs. jitter - steve weir
[SI-LIST] Re: passive component .vs. series component - Dmitriev-Zdorov, Vladimir
[SI-LIST] Re: f vs. Tf vs. jitter - Steven Kan
[SI-LIST] Re: SSTL_2 doubt - Kihong Kim
[SI-LIST] Job Opening at Spansion - Manoj Nachnani
[SI-LIST] Re: Diif pair geometry trade offs - Ken Cantrell
[SI-LIST] Re: Diif pair geometry trade offs - Scott McMorrow
[SI-LIST] Re: f vs. Tf vs. jitter - steve weir
[SI-LIST] Re: Diif pair geometry trade offs - Bill Owsley
[SI-LIST] Re: Diif pair geometry trade offs - Bill Owsley
[SI-LIST] Re: Diif pair geometry trade offs - Scott McMorrow
[SI-LIST] Re: Diif pair geometry trade offs - Aubrey_Sparkman
[SI-LIST] Re: HIGH DC Current on GND Plane - Eddy
[SI-LIST] Re: HIGH DC Current on GND Plane - steve weir
[SI-LIST] SI Tools - sunil bharadwaz
[SI-LIST] Re: SSTL_2 doubt - Canes Venatici
[SI-LIST] Re: SI Tools - Michael PARKER
[SI-LIST] Re: HIGH DC Current on GND Plane - istvan novak
[SI-LIST] FW: Re: HIGH DC Current on GND Plane - Shimko, Steven R.
[SI-LIST] Re: f vs. Tf vs. jitter - Andrew Ingraham
[SI-LIST] Re: HIGH DC Current on GND Plane - Andrew Ingraham
[SI-LIST] Re: HIGH DC Current on GND Plane - Ken Cantrell
[SI-LIST] Re: SSTL_2 doubt - Kihong Kim
[SI-LIST] Re: HIGH DC Current on GND Plane - Lee Ritchey
[SI-LIST] Re: FW: Re: HIGH DC Current on GND Plane - Lee Ritchey
[SI-LIST] Re: FW: Re: HIGH DC Current on GND Plane - Shawn Nikoukary
[SI-LIST] Re: HIGH DC Current on GND Plane - Eddy
[SI-LIST] Re: HIGH DC Current on GND Plane - Kevin G. Rhoads
[SI-LIST] Re: HIGH DC Current on GND Plane - Eric Bogatin
[SI-LIST] Re: HIGH DC Current on GND Plane - Vinu Arumugham
[SI-LIST] Re: HIGH DC Current on GND Plane - Kevin G. Rhoads
[SI-LIST] FW: FW: Re: HIGH DC Current on GND Plane - Shimko, Steven R.
[SI-LIST] Re: SI Tools - Gregory Kobidze
[SI-LIST] Re: HIGH DC Current on GND Plane - Nick Langston, Sr.
[SI-LIST] Re: HIGH DC Current on GND Plane - Bill Owsley
[SI-LIST] Re: HIGH DC Current on GND Plane - Lee Ritchey
[SI-LIST] Re: HIGH DC Current on GND Plane - Naftali Shani
[SI-LIST] Re: HIGH DC Current on GND Plane - Saravanabhavan C
[SI-LIST] Re: f vs. Tf vs. jitter - steve weir
[SI-LIST] Re: HIGH DC Current on GND Plane - steve weir
[SI-LIST] Re: HIGH DC Current on GND Plane - Istvan Novak
[SI-LIST] Re: f vs. Tf vs. jitter - Kihong Kim
[SI-LIST] HIGH DC Current on GND Plane - RameshK Cozerv IN HO
[SI-LIST] HIGH DC Current on GND Plane - RameshK Cozerv IN HO
[SI-LIST] Re: SSTL_2 doubt - Canes Venatici
[SI-LIST] SI and FAE engineer openings - John Lehman
[SI-LIST] free signal integrity analysis tools - Eric Bogatin
[SI-LIST] Convergence problem with DDR DRAM IBIS model - Ravinder . Ajmani
[SI-LIST] Re: free signal integrity analysis tools - Ray Anderson
[SI-LIST] Re: HIGH DC Current on GND Plane - Vinu Arumugham
[SI-LIST] Re: free signal integrity analysis tools - Istvan Novak
[SI-LIST] Re: free signal integrity analysis tools - Hargin, Bill
[SI-LIST] Re: free signal integrity analysis tools - Abe (Abbas) Riazi
[SI-LIST] Re: Characteristic Impedance - Andrew Byers
[SI-LIST] Re: Convergence problem with DDR DRAM IBIS model - Lynne D. Green
[SI-LIST] Re: HIGH DC Current on GND Plane - Istvan Novak
[SI-LIST] Re: Convergence problem with DDR DRAM IBIS model - Joseph Kao
[SI-LIST] Re: Convergence problem with DDR DRAM IBIS model - deltaboy
[SI-LIST] Matching Differntial Pairs - Kathy Jacques
[SI-LIST] SI Position in Austin, TX - Cheryl Blount
[SI-LIST] attachment test - Cliff Clark
[SI-LIST] Re: attachment test - Bill Owsley
[SI-LIST] How does multiple Ghz high speed signal behave on a sheet of conductor plane? - Dong Kim
[SI-LIST] Re: How does multiple Ghz high speed signal behave on a sheet of conductor plane? - steve weir
[SI-LIST] Re: How does multiple Ghz high speed signal behave on a sheet of conductor plane? - Ken Cantrell
[SI-LIST] DDR consecutive bits - OPREA Dorin
[SI-LIST] Re: Matching Differntial Pairs - Edi Fraiman
[SI-LIST] Re: free signal integrity analysis tools - Chris Cheng
[SI-LIST] step response simulators - Cliff Clark
[SI-LIST] Re: step response simulators - Paul Levin
[SI-LIST] DDR-400 T-topology and simulation questions - CR
[SI-LIST] why no class-I/II in SSTL_1.8 - Canes Venatici
[SI-LIST] Re: free signal integrity analysis tools - Luc Durand
[SI-LIST] Re: why no class-I/II in SSTL_1.8 - Alexandre . AMEDEO
[SI-LIST] Re: free signal integrity analysis tools - Dave Instone
[SI-LIST] Re: free signal integrity analysis tools - Ray Anderson
[SI-LIST] Asian IBIS Summit (China) Second Announcement - Bob Ross
[SI-LIST] USAGE OF TIE CELLS and TIE PINS - deepti maheshwari
[SI-LIST] Re: DDR-400 T-topology and simulation questions - Hans Klos
[SI-LIST] Re: DDR-400 T-topology and simulation questions - Hiten Bhagat
[SI-LIST] Asian IBIS Summit (Japan) First Announcement - Bob Ross
[SI-LIST] 12 port model with 4 port VNA - Simba Julian
[SI-LIST] Re: 12 port model with 4 port VNA - Jia Gongxian
[SI-LIST] Re: free signal integrity analysis tools - ROKI LERNER
[SI-LIST] Re: free signal integrity analysis tools - Tate, David
[SI-LIST] DC-blocking transmission-line - George Korony
[SI-LIST] Re: DC-blocking transmission-line - scott
[SI-LIST] Re: DC-blocking transmission-line - Terry Fox
[SI-LIST] FW: DC-blocking transmission-line - George Korony
[SI-LIST] Re: DC-blocking transmission-line - Bill Owsley
[SI-LIST] Re: DC-blocking transmission-line - Aubrey_Sparkman
[SI-LIST] digital circuits radiated emission as a function of VDD - jun feng
[SI-LIST] Re: digital circuits radiated emission as a function of VDD - olaney
[SI-LIST] Re: digital circuits radiated emission as a function of VDD - Townsend, Fred
[SI-LIST] Re: DC-blocking transmission-line - noting a lack of hi-lites I added in response - Bill Owsley
[SI-LIST] Re: digital circuits radiated emission as a function of VDD - Bill Owsley
[SI-LIST] Re: 12 port model with 4 port VNA - bratfest
[SI-LIST] Re: FW: DC-blocking transmission-line - Scott McMorrow
[SI-LIST] Re: DC-blocking transmission-line - steve weir
[SI-LIST] test - Koller, Katja
[SI-LIST] Job Opening at Wipro Technologies - praveen.srikantaiah
[SI-LIST] DC-blocking transmission-line - George Korony
[SI-LIST] Blank - George Korony
[SI-LIST] Re: DC-blocking transmission-line - Scott McMorrow
[SI-LIST] Re: DC-blocking transmission-line - olaney
[SI-LIST] Re: FW: DC-blocking transmission-line - Andrew Ingraham
[SI-LIST] Re: digital circuits radiated emission as a function of VDD - Andrew Ingraham
[SI-LIST] ATCS Field Applications Eng Position. - Kevin Ryan
[SI-LIST] Re: DC-blocking transmission-line - George Korony
[SI-LIST] Re: digital circuits radiated emission as a function of VDD - olaney
[SI-LIST] Re: FW: DC-blocking transmission-line - George Korony
[SI-LIST] Wolfgang Maichen/USW/Teradyne is out of the office. - wolfgang . maichen
[SI-LIST] Re: free signal integrity analysis tools - ROKI LERNER