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Thread Index for si-list, 06-2006

[si-list] || [06-2006 Date Index] [06-2006 Thread Index]

  1. [SI-LIST] Re: PCI-X (133Mhz) bus terminations, Peterson, James F \(FL51\)
  2. [SI-LIST] SSN can affect input behaviour?, Giovanni Guasti
  3. [SI-LIST] Re: SSN can affect input behaviour?, art_porter
  4. [SI-LIST] Running analog video on micro-coax, Joel Brown
  5. [SI-LIST] Re: Strange resets happening in one of our circuit boards, Chris Cheng
  6. [SI-LIST] Re: Running analog video on micro-coax, Leonard Dieguez
  7. [SI-LIST] Re: Copper balancing/ The process is called THIEVING, Salkow, Steven
  8. [SI-LIST] Re: Copper balancing, JaMi Smith
  9. [SI-LIST] Re: Question about split gnd planes, JaMi Smith
  10. [SI-LIST] Re: [SPAM] Re: Question about split gnd planes, JaMi Smith
  11. [SI-LIST] Re: gigabit ethernet trace length, Andrew Ingraham
  12. [SI-LIST] Dallas EMC Colloquium -- July 13, 2006, Ram Chundru
  13. [SI-LIST] Re: Running analog video on micro-coaxH, DrFWS
  14. [SI-LIST] How can mentor Boardstation interface with Ansoft SI-Wave ?, 이 상원
  15. [SI-LIST] What is the difference between ANA and VNA?, zhangkun 29902
  16. [SI-LIST] Measuring structural resonances for fun and relaxation (and work too), Doug Smith
  17. [SI-LIST] Reg: Buffer fanout, Marimuthu P.
  18. [SI-LIST] Re: How can mentor Boardstation interface with Ansoft SI-Wave ?, Antselovitch Joseph
  19. [SI-LIST] Re: AC coupling Capacitor (Eye Diagram Issue), jain.nitin
  20. [SI-LIST] SI-List Graphics or pics, Leonard Dieguez
  21. [SI-LIST] Recall: SI-List Graphics or pics, Leonard Dieguez
  22. [SI-LIST] Re: Recall: SI-List Graphics or pics, Mike Greim
  23. [SI-LIST] Re: SI-List Graphics or pics, Ray Anderson
  24. [SI-LIST] Re: measurement methods of power supply networks for a wirebond BGA package, Hill, John
  25. [SI-LIST] Signal Integrity Position @ PMC-Sierra, John Plasterer
  26. [SI-LIST] SPLIT POWER PLANE, sreekanth namboothiri
  27. [SI-LIST] Re: SPLIT POWER PLANE, Dharmendra Gowra
  28. [SI-LIST] Long trace open on the both ends, Ravinder . Ajmani
  29. [SI-LIST] Power/GND and fires, Shawn Arnold
  30. [SI-LIST] Re: Power/GND and fires, Chris Padilla \(cpad\)
  31. [SI-LIST] About Touchstone file, jliou
  32. [SI-LIST] Split GND Plane on PKG, jbtera77
  33. [SI-LIST] Re: Long trace open on the both ends, Nagaraju Nerella
  34. [SI-LIST] SDRAM Termination, Saril
  35. [SI-LIST] Re: SDRAM Termination, Dharmendra Gowra
  36. [SI-LIST] analog - digtal power, Kamran Azizi
  37. [SI-LIST] Package characterization, Vijay Chachra
  38. [SI-LIST] Re: Split GND Plane on PKG, Geoff Stokes
  39. [SI-LIST] Package characterisation, Eoin Mc Gibney
  40. [SI-LIST] Senior/lead SI engineer position @ Cisco San Jose, Bill Chen \(billchen\)
  41. [SI-LIST] Timing Analysis, vighneshrudra das
  42. [SI-LIST] Modelling radiation, Mark Burford
  43. [SI-LIST] Re: Modelling radiation, Chris Padilla \(cpad\)
  44. [SI-LIST] Re: RJ-45 Connector, Lee Ritchey
  45. [SI-LIST] Doug Unplugged!, Doug Smith
  46. [SI-LIST] FW: CIE/EPMC announcement - Dinner Seminar on 6/28, Jin Zhao
  47. [SI-LIST] Re: Signal Integrity issues at -40 degrees C, Andrew Drysdale
  48. [SI-LIST] about component modeling solution, "신연숙"
  49. [SI-LIST] Setup-Hold time, vighneshrudra das
  50. [SI-LIST] S-parameter passivity... Interpreting the results., travis ellis
  51. [SI-LIST] Re: S-parameter passivity... Interpreting the results., Hill, John
  52. [SI-LIST] Value of pull up resistors, sunil bharadwaz
  53. [SI-LIST] Digilog design and tesla coils, Doug Smith
  54. [SI-LIST] slow down the edges, Kamran Azizi
  55. [SI-LIST] Re: about component modeling solution, dmitry.a.smolyansky
  56. [SI-LIST] Re: Setup-Hold time, Dharmendra Gowra
  57. [SI-LIST] Inter-plane capacitance, Anupama
  58. [SI-LIST] Simulation models for Agilent 81250 ParBERT drivers, Buchs, Kevin J.
  59. [SI-LIST] simulating connectors in Hyperlynx, Joel Brown
  60. [SI-LIST] Re: Inter-plane capacitance, Grasso, Charles
  61. [SI-LIST] Re: simulating connectors in Hyperlynx, Corey Kimble
  62. [SI-LIST] Pre-emphasis Vs De-emphasis, Babid A
  63. [SI-LIST] Re: Pre-emphasis Vs De-emphasis, Ray Anderson
  64. [SI-LIST] Re: EMI, Xilei Liu
  65. [SI-LIST] CPW, sunil bharadwaz
  66. [SI-LIST] Re: CPW, Lee Ritchey
  67. [SI-LIST] How to get Intel IBIS models, Joel Brown
  68. [SI-LIST] Signal Integrity project in San Jose, CA, Kevin Pierpoint
  69. [SI-LIST] 8 bit async. parallel bus on back plane, Steve Lin
  70. [SI-LIST] Re: 8 bit async. parallel bus on back plane, Lee Ritchey
  71. [SI-LIST] PCI Bus, Khai K
  72. [SI-LIST] SDR SDRAM Layout, Kevin K
  73. [SI-LIST] Re: PCI Bus, zhangkun 29902
  74. [SI-LIST] 14 Layer Stackup, jain.nitin
  75. [SI-LIST] Signal Integrity and PCB layout positions for Cisco R&D center in CHINA (Shanghai, China), Bill Chen \(billchen\)
  76. [SI-LIST] Re: 14 Layer Stackup, Lee Ritchey
  77. [SI-LIST] Signal integrity position available at Hewlett Packard in Richardson, Texas, Richard Schumacher
  78. [SI-LIST] Strange non-monotonic edge after LVPECL and LVDS interface circuit, luping liu
  79. [SI-LIST] Undershoot or Overshoot Issue at Die Level, Dean Fitzgerald
  80. [SI-LIST] Shielding Question, Clewell, Craig
  81. [SI-LIST] Re: »Ø¸´£º Re: 14 Layer Stackup, Lee Ritchey
  82. [SI-LIST] Re: Shielding Question, Ken Holman
  83. [SI-LIST] Job Opening: IC Package Electrical Simulation & Modeling Engineer, Joiner Bennett-rxmn60
  84. [SI-LIST] Mictor Connectors, Kevin K
  85. [SI-LIST] Twisting of differential pair traces, Fonseca, Joaquin
  86. [SI-LIST] Re: Twisting of differential pair traces, jain.nitin
  87. [SI-LIST] What is imporatnt in a simulator?, Ing. Giancarlo Guida
  88. [SI-LIST] SI-related jobs at Sigrity, Raymond Y. Chen
  89. [SI-LIST] Re: What is important in a simulator?, Abe (Abbas) Riazi
  90. [SI-LIST] Re: What is imporatnt in a simulator?, Ming Tsai
  91. [SI-LIST] cat 6 RJ45 jack for PCB, jan . vercammen1
  92. [SI-LIST] Re: cat 6 RJ45 jack for PCB, Hill, John
  93. [SI-LIST] Re: Mictor Connectors, Chauhan, Prakash
  94. [SI-LIST] Digital PI/SI and RF SI/PI, Francis Matthew
  95. [SI-LIST] Rocket I/O models for hspice, Srivats Partha
  96. [SI-LIST] Re: Rocket I/O models for hspice, Giovanni Guasti
  97. [SI-LIST] SI openning at Marvell, Wei Zhou
  98. [SI-LIST] Signal Integrity Opening with Force10 Networks, Peter Tomaszewski
  99. [SI-LIST] sin(x)/x interpolation, Shoran
  100. [SI-LIST] DAC clock, Marimuthu P.
  101. [SI-LIST] Decoupling Capacitor ESR/ESL, Erin . McPhalen
  102. [SI-LIST] Feedback on graphic image, Steven Kan
  103. [SI-LIST] FW: SI Employment Opportunity at Altera: Posting, Larry Smith
  104. [SI-LIST] Re: Feedback on graphic image, dgun
  105. [SI-LIST] Re: sin(x)/x interpolation, art_porter
  106. [SI-LIST] spice question, Kamran Azizi
  107. [SI-LIST] Book, Narasimhan, Sarath (Sarath)
  108. [SI-LIST] Re: Decoupling Capacitor ESR/ESL, Lee Ritchey
  109. [SI-LIST] Re: Book, Giovanni Guasti
  110. [SI-LIST] DDR-2 memory models, Indira Gazula
  111. [SI-LIST] Trace Spacing Rule, Kevin K
  112. [SI-LIST] Re: PCB Reverse Engineering, Fred Townsend
  113. [SI-LIST] Re: DDR-2 memory models, Chauhan, Prakash
  114. [SI-LIST] Re: spice question, Tracy Barclay
  115. [SI-LIST] Mixed-mode impedance matrix, Zhou, Xingling \(Mick\)
  116. [SI-LIST] Re: Trace Spacing Rule, Lee Ritchey
  117. [SI-LIST] Re: Mixed-mode impedance matrix, Bill Beale
  118. [SI-LIST] Advantages of Pi termination network, Srivats Partha
  119. [SI-LIST] Fibre channel interconnect margins, Babid A
  120. [SI-LIST] Re: Fibre channel interconnect margins, Mcgrath, Christopher



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