FreeLists / si-list / [SI-LIST] 回复： Re: SDRAM Termination

[彬 龙 <alonger2002@xxxxxxxxxxxx>]

yes,You can do a simulation to fix the Termination ,But I have exeperience at 
such a Topology, CPU+Flash+SDRAM,No termination needed also OK. I have forgot 
the clock frequency for the flash,but the SDRAM is 133MHz, and you are 
right,make the SDRAM close to the CPU in the topology.regard the length and via 
for databus,it is best if they are identical....
   
  Luc Durand <luc.durand@xxxxxxxxxx> дµÀ£º
  Hello Saril,
Just use a good simulator. I personally use SpectraQuest from Cadence
but there are others as well. It allows the use of IBIS models so you
can place your topology with the required track lengths and try out
various termination strategy. You should be able to get an IBIS model of
your SDRAM and your Flash from the vendors.

Regards,

Luc Durand

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Saril
Sent: Wednesday, June 07, 2006 4:29 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SDRAM Termination


Hi,
=20
We have an External Memory Interface Bus, which is shared by Boot
FLASH and SDRAM memories. This triggers a Daisy chain topology, we
decided to use a 33 ohm series termination resistor near to the CPU bga
balls and route to SDRAM first, then take it to the FLASH. But there is
one more suggestion, put a 50ohm parallel termination ( trace impedance
is 50 ohm) to ground at the end of the trace near to FLASH, but it will
consume more current.
=20
Can anybody please give a good termination strategy for this Daisy
chain topology?
=20
Thanks and regards
Saril Kaiprath
Design Engineer
FDL
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