Date Index for si-list, 06-2006

[si-list] || [06-2006 Date Index] [06-2006 Thread Index]

[SI-LIST] Re: PCI-X (133Mhz) bus terminations - Peterson, James F \(FL51\)
[SI-LIST] SSN can affect input behaviour? - Giovanni Guasti
[SI-LIST] Re: SSN can affect input behaviour? - art_porter
[SI-LIST] Re: PCI-X (133Mhz) bus terminations - Kishan
[SI-LIST] Running analog video on micro-coax - Joel Brown
[SI-LIST] Re: Running analog video on micro-coax - Tom Dagostino
[SI-LIST] Strange resets happening in one of our circuit boards - Bashir, Shiraz \(GE Healthcare\)
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Chris Cheng
[SI-LIST] Re: Strange resets happening in one of our circuit boards - istvan.novak
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Bashir, Shiraz \(GE Healthcare\)
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Scott McMorrow
[SI-LIST] Re: Running analog video on micro-coax - Leonard Dieguez
[SI-LIST] Re: Running analog video on micro-coax - Tom Dagostino
[SI-LIST] Re: Strange resets happening in one of our circuit boards - istvan.novak
[SI-LIST] Re: Strange resets happening in one of our circuit boards - stubenner
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Zhangkun
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Zhangkun
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Salkow, Steven
[SI-LIST] Re: Copper balancing/ The process is called THIEVING - Salkow, Steven
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Doug Smith
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Doug Smith
[SI-LIST] Re: Running analog video on micro-coax - Nagaraju Nerella
[SI-LIST] Re: Copper balancing - JaMi Smith
[SI-LIST] Re: Question about split gnd planes - JaMi Smith
[SI-LIST] Re: [SPAM] Re: Question about split gnd planes - JaMi Smith
[SI-LIST] Re: [SPAM] Re: Question about split gnd planes - Kenneth W. Egan
[SI-LIST] Re: [SPAM] Re: Question about split gnd planes - steve weir
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Carlton Ross-ra8188
[SI-LIST] Re: Running analog video on micro-coax - Julian Ferry
[SI-LIST] Re: PCI-X (133Mhz) bus terminations - George Peterson
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Peterson, James F \(FL51\)
[SI-LIST] Re: Running analog video on micro-coax - Andrew Ingraham
[SI-LIST] Re: Strange resets happening in one of our circuit boards - m . j . farrell
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Andrew Ingraham
[SI-LIST] Re: gigabit ethernet trace length - Andrew Ingraham
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Lynne D. Green
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Nima Lotfi
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Grasso, Charles
[SI-LIST] Re: Running analog video on micro-coax - Tom Dagostino
[SI-LIST] Dallas EMC Colloquium -- July 13, 2006 - Ram Chundru
[SI-LIST] Re: PCI-X (133Mhz) bus terminations - Chris Cheng
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Eric Goodill
[SI-LIST] Re: [SPAM] Re: Question about split gnd planes - Tom Dagostino
[SI-LIST] Re: Running analog video on micro-coaxH - DrFWS
[SI-LIST] Re: [SPAM] Re: Question about split gnd planes - Kenneth W. Egan
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Andrew Ingraham
[SI-LIST] How can mentor Boardstation interface with Ansoft SI-Wave ? - 이 상원
[SI-LIST] Re: [SPAM] Re: Question about split gnd planes - JaMi Smith
[SI-LIST] What is the difference between ANA and VNA? - zhangkun 29902
[SI-LIST] Measuring structural resonances for fun and relaxation (and work too) - Doug Smith
[SI-LIST] Reg: Buffer fanout - Marimuthu P.
[SI-LIST] Re: How can mentor Boardstation interface with Ansoft SI-Wave ? - Antselovitch Joseph
[SI-LIST] Re: AC coupling Capacitor (Eye Diagram Issue) - jain.nitin
[SI-LIST] Re: AC coupling Capacitor (Eye Diagram Issue) - Stephen Zinck
[SI-LIST] SI-List Graphics or pics - Leonard Dieguez
[SI-LIST] Recall: SI-List Graphics or pics - Leonard Dieguez
[SI-LIST] Recall: SI-List Graphics or pics - Leonard Dieguez
[SI-LIST] Re: Recall: SI-List Graphics or pics - Mike Greim
[SI-LIST] Re: SI-List Graphics or pics - Ray Anderson
[SI-LIST] Re: SI-List Graphics or pics - Mark Randol
[SI-LIST] Re: measurement methods of power supply networks for a wirebond BGA package - Hill, John
[SI-LIST] Job Opening - PHY Applications Engineer @ Broadcom - npischl
[SI-LIST] Signal Integrity Position @ PMC-Sierra - John Plasterer
[SI-LIST] AW: How can mentor Boardstation interface with Ansoft SI-Wave ? - Gerd Prillwitz
[SI-LIST] Re: :Is mini PCI and PCI are compatable to interface with each other - avulab
[SI-LIST] SPLIT POWER PLANE - sreekanth namboothiri
[SI-LIST] Re: SPLIT POWER PLANE - Dharmendra Gowra
[SI-LIST] Re: SPLIT POWER PLANE - avulab
[SI-LIST] Re: What is the difference between ANA and VNA? - Peter Fekete
[SI-LIST] Re: Running analog video on micro-coax - Hill, John
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Hill, John
[SI-LIST] Long trace open on the both ends - Ravinder . Ajmani
[SI-LIST] Power/GND and fires - Shawn Arnold
[SI-LIST] Re: Power/GND and fires - Chris Padilla \(cpad\)
[SI-LIST] About Touchstone file - jliou
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Doug Smith
[SI-LIST] Split GND Plane on PKG - jbtera77
[SI-LIST] Re: Long trace open on the both ends - Nagaraju Nerella
[SI-LIST] SDRAM Termination - Saril
[SI-LIST] Re: SDRAM Termination - Luc Durand
[SI-LIST] 回复： Re: SDRAM Termination - 彬 龙
[SI-LIST] Re: SDRAM Termination - Stephen Zinck
[SI-LIST] Re: Strange resets happening in one of our circuit boards - Hill, John
[SI-LIST] Re: Long trace open on the both ends - Lee Ritchey
[SI-LIST] Re: Power/GND and fires - Lee Ritchey
[SI-LIST] Re: Long trace open on the both ends - Ravinder . Ajmani
[SI-LIST] Re: About Touchstone file - Ing. Giancarlo Guida
[SI-LIST] Re: Split GND Plane on PKG - Alan . Hiltonnickel
[SI-LIST] Re: SDRAM Termination - Dharmendra Gowra
[SI-LIST] analog - digtal power - Kamran Azizi
[SI-LIST] Package characterization - Vijay Chachra
[SI-LIST] Re: Split GND Plane on PKG - Geoff Stokes
[SI-LIST] Package characterisation - Eoin Mc Gibney
[SI-LIST] Re: SDRAM Termination - Saril
[SI-LIST] Re: SDRAM Termination - Lee Ritchey
[SI-LIST] R: Package characterization - gianguida
[SI-LIST] Senior/lead SI engineer position @ Cisco San Jose - Bill Chen \(billchen\)
[SI-LIST] RJ-45 Connector - Chandupcb
[SI-LIST] Timing Analysis - vighneshrudra das
[SI-LIST] Re: Timing Analysis - Saril
[SI-LIST] Modelling radiation - Mark Burford
[SI-LIST] Re: Modelling radiation - Chris Padilla \(cpad\)
[SI-LIST] Re: RJ-45 Connector - Lee Ritchey
[SI-LIST] Re: RJ-45 Connector - Curt McNamara
[SI-LIST] Re: RJ-45 Connector - Lee Ritchey
[SI-LIST] Re: RJ-45 Connector - Chris Padilla \(cpad\)
[SI-LIST] Re: RJ-45 Connector - Curt McNamara
[SI-LIST] Re: RJ-45 Connector - Joel Brown
[SI-LIST] Re: RJ-45 Connector - Curt McNamara
[SI-LIST] Re: RJ-45 Connector - Curt McNamara
[SI-LIST] Re: RJ-45 Connector - Curt McNamara
[SI-LIST] Re: RJ-45 Connector - Joel Brown
[SI-LIST] Re: RJ-45 Connector - Tom Dagostino
[SI-LIST] Re: RJ-45 Connector - Lee Ritchey
[SI-LIST] Re: RJ-45 Connector - Curt McNamara
[SI-LIST] Re: RJ-45 Connector - Lee Ritchey
[SI-LIST] Re: RJ-45 Connector - Tom Dagostino
[SI-LIST] Re: RJ-45 Connector - Zhangkun
[SI-LIST] Doug Unplugged! - Doug Smith
[SI-LIST] FW: CIE/EPMC announcement - Dinner Seminar on 6/28 - Jin Zhao
[SI-LIST] Re: Signal Integrity issues at -40 degrees C - Andrew Drysdale
[SI-LIST] about component modeling solution - "신연숙"
[SI-LIST] Setup-Hold time - vighneshrudra das
[SI-LIST] S-parameter passivity... Interpreting the results. - travis ellis
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - Hill, John
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - Xilei Liu
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - travis ellis
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - Aubrey_Sparkman
[SI-LIST] Value of pull up resistors - sunil bharadwaz
[SI-LIST] Re: Value of pull up resistors - Tom Dagostino
[SI-LIST] Re: Value of pull up resistors - Suren
[SI-LIST] Digilog design and tesla coils - Doug Smith
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - Hill, John
[SI-LIST] slow down the edges - Kamran Azizi
[SI-LIST] Re: about component modeling solution - dmitry.a.smolyansky
[SI-LIST] Re: Setup-Hold time - Dharmendra Gowra
[SI-LIST] Inter-plane capacitance - Anupama
[SI-LIST] Re: Inter-plane capacitance - steve weir
[SI-LIST] Simulation models for Agilent 81250 ParBERT drivers - Buchs, Kevin J.
[SI-LIST] R: Inter-plane capacitance - gianguida
[SI-LIST] Re: Value of pull up resistors - Andrew Ingraham
[SI-LIST] simulating connectors in Hyperlynx - Joel Brown
[SI-LIST] Re: Inter-plane capacitance - Grasso, Charles
[SI-LIST] Re: simulating connectors in Hyperlynx - Corey Kimble
[SI-LIST] Re: simulating connectors in Hyperlynx - Joel Brown
[SI-LIST] Re: slow down the edges - Kai Keskinen
[SI-LIST] Re: Inter-plane capacitance - Kai Keskinen
[SI-LIST] Re: Inter-plane capacitance - Istvan Novak - Board Design Technology
[SI-LIST] Pre-emphasis Vs De-emphasis - Babid A
[SI-LIST] Re: Pre-emphasis Vs De-emphasis - Ray Anderson
[SI-LIST] Re: Pre-emphasis Vs De-emphasis - Mohammad Ali
[SI-LIST] Re: simulating connectors in HyperLynx - Carrier, Patrick
[SI-LIST] Re: Setup-Hold time - Jai Shanker
[SI-LIST] Re: Pre-emphasis Vs De-emphasis - sivi\.cla\@libero\.it
[SI-LIST] EMI - shekhar sharma
[SI-LIST] Re: EMI - Powell, Doug
[SI-LIST] Re: EMI - Xilei Liu
[SI-LIST] CPW - sunil bharadwaz
[SI-LIST] Re: EMI - Doug Brooks
[SI-LIST] Re: CPW - Tom Dagostino
[SI-LIST] Re: CPW - Xilei Liu
[SI-LIST] Re: CPW - Chris Reid
[SI-LIST] Re: CPW - Lee Ritchey
[SI-LIST] Re: CPW - steve weir
[SI-LIST] R: CPW - gianguida
[SI-LIST] Re: EMI - steve weir
[SI-LIST] How to get Intel IBIS models - Joel Brown
[SI-LIST] Re: How to get Intel IBIS models - Aubrey_Sparkman
[SI-LIST] Signal Integrity project in San Jose, CA - Kevin Pierpoint
[SI-LIST] 8 bit async. parallel bus on back plane - Steve Lin
[SI-LIST] Re: R: CPW - sunil bharadwaz
[SI-LIST] Re: 8 bit async. parallel bus on back plane - Lee Ritchey
[SI-LIST] Re: 8 bit async. parallel bus on back plane - steve weir
[SI-LIST] Re: How to get Intel IBIS models - Kai Keskinen
[SI-LIST] Re: EMI - Kai Keskinen
[SI-LIST] Re: 8 bit async. parallel bus on back plane - asparkman
[SI-LIST] Re: 8 bit async. parallel bus on back plane - Steve Lin
[SI-LIST] PCI Bus - Khai K
[SI-LIST] SDR SDRAM Layout - Kevin K
[SI-LIST] Re: PCI Bus - steve weir
[SI-LIST] Re: SDR SDRAM Layout - steve weir
[SI-LIST] Re: PCI Bus - zhangkun 29902
[SI-LIST] Re: PCI Bus - msmurthy murthy
[SI-LIST] Re: PCI Bus - Xilei Liu
[SI-LIST] 14 Layer Stackup - jain.nitin
[SI-LIST] Signal Integrity and PCB layout positions for Cisco R&D center in CHINA (Shanghai, China) - Bill Chen \(billchen\)
[SI-LIST] Re: 14 Layer Stackup - steve weir
[SI-LIST] Re: 14 Layer Stackup - Lee Ritchey
[SI-LIST] Re: 14 Layer Stackup - jain.nitin
[SI-LIST] Re: 14 Layer Stackup - Xilei Liu
[SI-LIST] Re: PCI Bus - Andrew Ingraham
[SI-LIST] Signal integrity position available at Hewlett Packard in Richardson, Texas - Richard Schumacher
[SI-LIST] 回复： Re: 14 Layer Stackup - 彬 龙
[SI-LIST] Strange non-monotonic edge after LVPECL and LVDS interface circuit - luping liu
[SI-LIST] Undershoot or Overshoot Issue at Die Level - Dean Fitzgerald
[SI-LIST] Re: Undershoot or Overshoot Issue at Die Level - Aubrey_Sparkman
[SI-LIST] Shielding Question - Clewell, Craig
[SI-LIST] Re: 14 Layer Stackup - Lee Ritchey
[SI-LIST] Re: 14 Layer Stackup - Lee Ritchey
[SI-LIST] Re: »Ø¸´£º Re: 14 Layer Stackup - Lee Ritchey
[SI-LIST] Re: Shielding Question - Xilei Liu
[SI-LIST] Re: Shielding Question - Ken Holman
[SI-LIST] Re: Signal Integrity and PCB layout positions for Cisco R&D center in CHINA (Shanghai, China) - Oscar Lang
[SI-LIST] 回复： RE: 回复： Re: 14 Layer Stackup - 彬 龙
[SI-LIST] Re: Shielding Question - Hill, John
[SI-LIST] Job Opening: IC Package Electrical Simulation & Modeling Engineer - Joiner Bennett-rxmn60
[SI-LIST] Mictor Connectors - Kevin K
[SI-LIST] Twisting of differential pair traces - Fonseca, Joaquin
[SI-LIST] Re: Twisting of differential pair traces - jain.nitin
[SI-LIST] What is imporatnt in a simulator? - Ing. Giancarlo Guida
[SI-LIST] SI-related jobs at Sigrity - Raymond Y. Chen
[SI-LIST] Re: What is imporatnt in a simulator? - Kai Keskinen
[SI-LIST] Re: What is important in a simulator? - Abe (Abbas) Riazi
[SI-LIST] Re: What is imporatnt in a simulator? - Ming Tsai
[SI-LIST] Re: What is imporatnt in a simulator? - Xilei Liu
[SI-LIST] cat 6 RJ45 jack for PCB - jan . vercammen1
[SI-LIST] Re: cat 6 RJ45 jack for PCB - steve weir
[SI-LIST] Re: cat 6 RJ45 jack for PCB - Hill, John
[SI-LIST] Re: Mictor Connectors - Jim Antonellis
[SI-LIST] Re: Mictor Connectors - Chauhan, Prakash
[SI-LIST] Re: cat 6 RJ45 jack for PCB - Mikhail Matusov
[SI-LIST] Re: cat 6 RJ45 jack for PCB - JaMi Smith
[SI-LIST] Re: Twisting of differential pair traces - Nitin Sood
[SI-LIST] Re: Mictor Connectors - Nitin Sood
[SI-LIST] Digital PI/SI and RF SI/PI - Francis Matthew
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - dgun
[SI-LIST] Rocket I/O models for hspice - Srivats Partha
[SI-LIST] Re: Rocket I/O models for hspice - Giovanni Guasti
[SI-LIST] Re: cat 6 RJ45 jack for PCB - Thomas Beneken
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - Xilei Liu
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - Hill, John
[SI-LIST] SI openning at Marvell - Wei Zhou
[SI-LIST] Signal Integrity Opening with Force10 Networks - Peter Tomaszewski
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - Xilei Liu
[SI-LIST] how to model the via in Sigexplorer610 - Vigneshwara Upadhyaya
[SI-LIST] sin(x)/x interpolation - Shoran
[SI-LIST] Re: sin(x)/x interpolation - steve weir
[SI-LIST] DAC clock - Marimuthu P.
[SI-LIST] Re: sin(x)/x interpolation - Xilei Liu
[SI-LIST] Re: DAC clock - Mikhail Matusov
[SI-LIST] Decoupling Capacitor ESR/ESL - Erin . McPhalen
[SI-LIST] Feedback on graphic image - Steven Kan
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - steve weir
[SI-LIST] FW: SI Employment Opportunity at Altera: Posting - Larry Smith
[SI-LIST] Re: how to model the via in Sigexplorer610 - Kai Keskinen
[SI-LIST] Altera Netseminar on Singal Integrity, June 28 - Binshen Meng
[SI-LIST] Re: Feedback on graphic image - dgun
[SI-LIST] Re: Feedback on graphic image - Xilei Liu
[SI-LIST] Re: sin(x)/x interpolation - Andrew Ingraham
[SI-LIST] Re: sin(x)/x interpolation - art_porter
[SI-LIST] Re: Feedback on graphic image - Gary Morrell
[SI-LIST] spice question - Kamran Azizi
[SI-LIST] Book - Narasimhan, Sarath (Sarath)
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - Erin . McPhalen
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - Lee Ritchey
[SI-LIST] Re: Book - Giovanni Guasti
[SI-LIST] Re: how to model the via in Sigexplorer610 - Kai Keskinen
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - steve weir
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - steve weir
[SI-LIST] DDR-2 memory models - Indira Gazula
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - Lee Ritchey
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - steve weir
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - Erin . McPhalen
[SI-LIST] Re: measurement methods of power supply networks for a wirebond BGA package - Hill, John
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - Lee Ritchey
[SI-LIST] Re: Decoupling Capacitor ESR/ESL - istvan.novak
[SI-LIST] Trace Spacing Rule - Kevin K
[SI-LIST] Re: measurement methods of power supply networks for a wirebond BGA package - Hill, John
[SI-LIST] Re: Trace Spacing Rule - steve weir
[SI-LIST] Re: PCB Reverse Engineering - Fred Townsend
[SI-LIST] Re: DDR-2 memory models - Chauhan, Prakash
[SI-LIST] Re: spice question - Tracy Barclay
[SI-LIST] Re: Trace Spacing Rule - Erin . McPhalen
[SI-LIST] Mixed-mode impedance matrix - Zhou, Xingling \(Mick\)
[SI-LIST] Re: S-parameter passivity... Interpreting the results. - Hill, John
[SI-LIST] Re: Trace Spacing Rule - Lee Ritchey
[SI-LIST] Re: Trace Spacing Rule - Lee Ritchey
[SI-LIST] Re: Mixed-mode impedance matrix - Scott McMorrow
[SI-LIST] Re: Mixed-mode impedance matrix - Zhou, Xingling \(Mick\)
[SI-LIST] Re: Mixed-mode impedance matrix - Xilei Liu
[SI-LIST] Re: Mixed-mode impedance matrix - Yuriy Shlepnev
[SI-LIST] Re: Mixed-mode impedance matrix - Bill Beale
[SI-LIST] Advantages of Pi termination network - Srivats Partha
[SI-LIST] Re: Advantages of Pi termination network - steve weir
[SI-LIST] Re: Mixed-mode impedance matrix - Zhou, Xingling \(Mick\)
[SI-LIST] Re: Mixed-mode impedance matrix - Zhou, Xingling \(Mick\)
[SI-LIST] Re: Mixed-mode impedance matrix - Zhou, Xingling \(Mick\)
[SI-LIST] Re: Mixed-mode impedance matrix - Yuriy Shlepnev
[SI-LIST] Re: Mixed-mode impedance matrix - Yuriy Shlepnev
[SI-LIST] Re: Mixed-mode impedance matrix - Zhou, Xingling \(Mick\)
[SI-LIST] Fibre channel interconnect margins - Babid A
[SI-LIST] Re: Fibre channel interconnect margins - Mcgrath, Christopher
[SI-LIST] Re: Trace Spacing Rule - Loyer, Jeff