FreeLists / si-list / [SI-LIST] IEEE CPMT Society Phoenix Chapter - June 29 meeting announcement

[Sam Karikalan <sam_karikalan@xxxxxxxxx>]

Greetings! This message is posted on behalf of IEEE
CPMT Society Phoenix Chapter:
-------------------------------------------------------The
Institute of Electrical and Electronics Engineers,
Inc.
Components, Packaging and Manufacturing Technology
Society - Phoenix Chapter
-------------------------------------------------------June
2004 meeting announcement
-----------------------------------------------------
Speaker: Mr. Tom Tarter, Neophotonics Corp., San Jose,
CA
Topic: Integration of Planar Light Wave Circuits
Date: June 29, 2004, Tuesday
Time: 5:30-6:00 pm Social/Refreshments, 6:00-7:00 pm
Presentation, 7:00 pm Dinner
Venue: Freescale Semiconductor (formerly Motorola
SPS), 2100 E Elliott Road, Tempe AZ

Abstract

Planar optical waveguide based light wave circuits
play a major role in low cost and high volume optical
component manufacturing in the telecommunications
industry.  The promise of optical waveguide chips
using the planar manufacturing technique is to provide
a solution to integrate multiple optical components
into a single chip platform, thus reducing the cost by
mass manufacturing and increasing the yield and
reliability of the device.  
In silica on silicon optical waveguides, the optical
properties of devices can or must be controlled
thermally. For example, optical waveguide based
switches and variable attenuators are controlled by
thermal optics through thin film heaters fabricated on
the waveguide photonic chip.  The center wavelength of
arrayed waveguides is controlled by heater or
heat/cool combinations depending on the application
environment. Thermal issues also become primary
obstacles when integrating several optical components
into a single-chip design.  Temperature control of
waveguides is critical and must be controlled to
within a few tenths of a degree C over a large ambient
operating range.  Materials used in the assembly of
these devices when packaged also must be carefully
evaluated for heat transfer and mechanical
characteristics.  Interaction of devices on the single
substrate must be managed with long-term effects in
mind and rigorous design, modeling, test and
validation are required for a viable product offering.

This talk centers on integrating heaters onto the chip
grating, to provide a solution path for integration of
multiple optical devices on a single substrate from a
thermo-mechanical as well as optical discipline point
of view.

Biography 

Tom Tarter is a noted expert in the area of thermal
management and electrical characterization of
packaging structures, both in microelectronic and
optoelectronic regimes. He spent over 16 years at
Advanced Micro Devices, in package characterization
and left as a Senior Member of the Technical Staff.
After a short time as Director of BGA Package
Engineering and Design at Advanced Interconnect
Technology (Pleasanton, CA) he is now responsible for
thermal management, temperature control, and package
development at Neo Photonics Corporation, San Jose,
CA. Tom has authored or co-authored over 20 published
papers and numerous short courses and lectures on
thermal and electrical phenomenon in microelectronic
packaging and most recently in optoelectronic
packaging. He has also lectured at graduate level
short courses at UC Santa Cruz extension and San Jose
State University. Tom chaired the JEDEC JC15.1 task
group on thermal standards for five years, and was
general chair of the JC15 thermal and electrical
characterization standards group for two years. He was
general chair of the semiconductor heat transfer
conference SemiTherm XIII, and serves on the executive
committee of SemiTherm to date. He is also technical
program chair for SEMI/CPMT-International Electronics
Manufacturing Technology Conference 2004 and was the
technical program chair for Wescon 2003. Tom is
currently the chapter chair for the IEEE Silicon
Valley Chapter of CPMT. 

IEEE members and non-members all are welcome to
attend.

Best Regards,
Sam Karikalan,
Program Chair - IEEE CPMT Society Phoenix Chapter

ST Assembly Test Services, Inc.
1711 W Greentree Dr., Suite 117,
Tempe AZ 85284
Tel.480-222-1722
e-mail: karikalans@xxxxxxxxxxx


        
                
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