FreeLists / si-list / [SI-LIST] Re: resend - Specctraquest model: mounted inductance

["Bart Bouma" <bart.bouma@xxxxxxxxx>]

Istvan,
thank you very much for your explanation.
The socalled attached inductance seems to be the inductance I need for 
simulations.
Should I use this attached inductance as the "intrinsic inductance" of the 
Specctraquest model?
> For both of the above reasons,
the loop inductance MINUS the plane inductance is the proper value for
simulations.  I call it attached inductance.

> With agressive mounting of a two-terminal
capacitor, the loop inductance can be much below the partial self
inductance of the capacitor body.  As it was also pointed out earlier, 
what
you really need to use in simulation is not the loop inductance associated 
with
the capacitor, because it contains the contribution from the plane 
inductance,
and it would be double counted.

Q: I assumed that the loopinductance consisted of the total inductance of 
the whole loop, including the capacitor.
Is my assumption wrong then? Is the definition of loop inductance equal to 
total inductance excluding the capacitor?

Q: then, how to specify ESL for  ceramic capacitors, both standard 
2-terminal and 3-terminal ones?
My idea: ESL = equivalent series inductance and should reflect the partial 
inductance of the device.
From your answer I understand, but correct me when I'm wrong,  that when 
we measure the ESL of a capacitor we actually measure the "loop inductance 
associated with the capacitor", thus including plane inductance.
When measured in a de-embedded fixture, don't we measure the capacitor's 
partial inductance then?

And finally: isn't this partial inductance more or less the same as my 
definition of intrinsic inductance, solely the inductance of the capacitor 
body?

Bart Bouma
http://www.yageo.com



Bart,

> - I only can assume that what you wrote is correct. I'm not a 
si-engineer,
> but a rf-guy and consequently think rf-wise.
> Does this mean that the impedance associated with all the vertical
> connections between the planes and the X2Y is dominant?
> How to deal then with those multiple terminal devices? Do they have an
> advantage by the fact that they have multiple parallel vertical
> connections?
> What about using multiple vias for X2Y or e.g. reversed geometry devices
> as an 0306 MLCC. Will this help to provide a low impedance to the 
planes?

As Nick pointed out, the vertical connection may not be dominant, but it 
is
an
inseparable part of the picture.  Because the presence of a PCB plane
under the capacitor will create a strong coupling between the bottom side
of the cap and the plane, the loop inductance becomes smaller, and
even though the vertical via inductance (the partial self inductance of 
via)
may approach zero, this diminishing via inductance will come together with
a reduction of loop inductance.  With agressive mounting of a two-terminal
capacitor, the loop inductance can be much below the partial self
inductance of the capacitor body.  As it was also pointed out earlier, 
what
you
really need to use in simulation is not the loop inductance associated 
with
the
capacitor, because it contains the contribution from the plane inductance,
and it
would be double counted.  More importantly, you will find that for the 
same
piece of capacitor, with the same exact pad and via geometry, the loop
inductance is a function of the capacitor's location on the plane, because
the
plane inductance is location dependent.  For both of the above reasons,
the loop inductance MINUS the plane inductance is the proper value for
simulations.  I call it attached inductance.  The attached inductance is
much
less dependent (ideally it is independent) of the capacitors location on 
the
plane.  The attached inductance value does depend on the construction of
the capacitor body, but even more importantly it depends on the connection
to the planes.  With a two-terminal capacitor, the attached inductance can
easily vary in a one-to-ten range, depending on pad and via geometry and
on the location of the closest plane with respect to the capacitor.

Best regards,

Istvan Novak
SUN Microsystems


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