Date Index for si-list, 06-2003

[si-list] || [06-2003 Date Index] [06-2003 Thread Index]

[SI-LIST] VNA Question - JP
[SI-LIST] Re: VNA Question - istvan novak
[SI-LIST] Re: (No Date: Mon, 2 Jun 2003 08:35:29 -0400 - Robert Kezer
[SI-LIST] Re: [Ethernet models and simulation] - Painter, Chris
[SI-LIST] Effective dielectric constant - atifshamim khan
[SI-LIST] Re: PCI Bus Routing - SI Eng
[SI-LIST] gtl signal ? - Nimish Aggarwal
[SI-LIST] resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Re: VNA Question - JP
[SI-LIST] Common Mode and Differential Termination - sunil-chandra . kasanyal
[SI-LIST] Flash with JTAG ISP - Siva kumar
[SI-LIST] Caps of plane pairs - Zhangkun
[SI-LIST] Re: gtl signal ? - Dunbar, Tony
[SI-LIST] Flash with JTAG ISP - Dimiter Popoff
[SI-LIST] Re: Caps of plane pairs - =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?=
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Roy Leventhal
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Larry Smith
[SI-LIST] Re: Flash with JTAG ISP - Michael Poimboeuf
[SI-LIST] Re: Effective dielectric constant - Ed Sayre III
[SI-LIST] Fluorosilicone - Moeller, Merrick
[SI-LIST] Re: Crystal Oscillator Overtones. - Parthasarathy Sampath
[SI-LIST] Re: Mixed signal: partitioning GND or unique plane ? - Javier DeLaCruz
[SI-LIST] Re: PCI Bus Routing - MikonCons
[SI-LIST] About the Cref in IBIS Model - cheng yin
[SI-LIST] Re: About the Cref in IBIS Model - Abdulrahman Rafiq
[SI-LIST] gtl signal - Nimish Aggarwal
[SI-LIST] Re: gtl signal - e.sweetman
[SI-LIST] searching for board-to-board connector with high vibration and shock resistance - Nico Fleurinck
[SI-LIST] Antw: searching for board-to-board connector withhigh vibration and shock resistance - Robert Nowak
[SI-LIST] Re: Caps of plane pairs - Thomas Beneken
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Re: About the Cref in IBIS Model - james . f . peterson
[SI-LIST] More inexpensive test equipment - Doug Smith
[SI-LIST] RMCEMC presentation downloads and meeting announcement. - Grasso, Charles
[SI-LIST] Networking help for PCB Designer - Bob McCreight
[SI-LIST] FW: HCA MEETING REMINDER - June 5, 2003 - jeff_latourrette
[SI-LIST] Re: Common Mode and Differential Termination - David Anthony
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Larry Smith
[SI-LIST] Embedded Systems Developers User Group - Adeel Malik
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Hspice: Flicker Noise of MOS - Himanshu Arora
[SI-LIST] POSSIBLE VIRUS ALERT: RE: Re: Power supply noise - Jon Powell
[SI-LIST] POSSIBLE VIRUS ALERT: RE: Re: Power supply noise - Sandor Daranyi
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Larry Smith
[SI-LIST] [RE]Impulse response of MMF - jina
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Report Creators - Rich Peyton
[SI-LIST] Re: Report Creators - Keskinen, Kai
[SI-LIST] Re: Report Creators - Bart Bouma
[SI-LIST] Re: Report Creators - Michael J. Degerstrom
[SI-LIST] hspice ploting (print) time limits - bpanos
[SI-LIST] Re: hspice ploting (print) time limits - bpanos
[SI-LIST] Re: hspice ploting (print) time limits - Clewell, Craig
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Grasso, Charles
[SI-LIST] Re: hspice ploting (print) time limits - Muranyi, Arpad
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Larry Smith
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - istvan novak
[SI-LIST] broadside coupled striplines - Paolo Peruzzi
[SI-LIST] Re: broadside coupled striplines - Martyn Gaudion
[SI-LIST] IBIS Timing Analysis - ndempshe
[SI-LIST] Re: IBIS Timing Analysis - Jon Powell
[SI-LIST] Re: IBIS Timing Analysis - Beal, Weston
[SI-LIST] Re: Report Creators - Jack Stone
[SI-LIST] Re: Report Creators - Kim Helliwell
[SI-LIST] Re: Report Creators - Michael Poimboeuf
[SI-LIST] Re: IBIS Timing Analysis - Robert Haller
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Re: resend - Specctraquest model: mounted inductanc e - Bart Bouma
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] delay vs. transmission line length - Yoni Tzafrir
[SI-LIST] Re: delay vs. transmission line length - Clewell, Craig
[SI-LIST] Re: delay vs. transmission line length - Yoni Tzafrir
[SI-LIST] Re: delay vs. transmission line length - Steve Horne
[SI-LIST] Re: delay vs. transmission line length - Dorin
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Nick
[SI-LIST] Re: delay vs. transmission line length - Jon Powell
[SI-LIST] Re: Report Creators - Feldman, Richard
[SI-LIST] Re: Report Creators - Rich Peyton
[SI-LIST] Re: delay vs. transmission line length - Raymond . Leung
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - istvan novak
[SI-LIST] Re: [RE]Impulse response of MMF - implementing FO models in SPICE - Ashok Prabhu M
[SI-LIST] Hspice simulator for board designs - Sidney S
[SI-LIST] Re: Report Creators - Jack Stone
[SI-LIST] Re: Hspice simulator for board designs - Guasti Giovanni
[SI-LIST] Re: Report Creators - Jack Stone
[SI-LIST] Re: Hspice simulator for board designs - Scott McMorrow
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] PCI Question - Gary Levin
[SI-LIST] PCI 4.3.6.2. System Board Impedance - Gary Levin
[SI-LIST] Re: delay vs. transmission line length - art_porter
[SI-LIST] Re: Report Creators - Bill Reams
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Nick
[SI-LIST] Re: Report Creators - Yu Liu
[SI-LIST] Re: Report Creators - Bill Reams
[SI-LIST] Re: Report Creators - Rich Peyton
[SI-LIST] Re: Hspice simulator for board designs - Douglas Burns
[SI-LIST] Re: PCI 4.3.6.2. System Board Impedance - k EPD
[SI-LIST] Re: Hspice simulator for board designs - David Kaiser
[SI-LIST] Re: Report Creators - Bill Reams
[SI-LIST] Re: Report Creators - Salkow, Steven
[SI-LIST] Re: Report Creators - Muranyi, Arpad
[SI-LIST] Overshoot and Undershoot Measurement Specification Question - Ken Tan
[SI-LIST] Re: delay vs. transmission line length - Raymond . Leung
[SI-LIST] Re: delay vs. transmission line length - Scott McMorrow
[SI-LIST] Re: Report Creators - Todd Westerhoff
[SI-LIST] Re: delay vs. transmission line length - Tabatchnick, Justin
[SI-LIST] Importing Device pad netlists and design kits spice models into ADS - Tabatchnick, Justin
[SI-LIST] Re: delay vs. transmission line length - Raymond . Leung
[SI-LIST] Re: delay vs. transmission line length - Raymond . Leung
[SI-LIST] Re: delay vs. transmission line length - Yoni Tzafrir
[SI-LIST] Re: Report Creators - Bart Bouma
[SI-LIST] Re: Hspice simulator for board designs - Guasti Giovanni
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Standard Interfacing techniques fo quartzr crystal oscillators - Adeel Malik
[SI-LIST] Re: Standard Interfacing techniques fo quartzr crystal oscillators - Ken Hartman
[SI-LIST] Re: Overshoot and Undershoot Measurement Specification Question - Ingraham, Andrew
[SI-LIST] SPECCTRAQuest vs. HyperLynx - Ravinder Ajmani
[SI-LIST] Re: SPECCTRAQuest vs. HyperLynx - Kim Helliwell
[SI-LIST] Re: SPECCTRAQuest vs. HyperLynx - Zhen Mu
[SI-LIST] Re: Crystal Oscillator Overtones. - Parthasarathy Sampath
[SI-LIST] Re: SPECCTRAQuest vs. HyperLynx - Subramanya C K
[SI-LIST] How do we choose the proper test load? - C.Y. Cheng
[SI-LIST] Re: How do we choose the proper test load? - Jon Powell
[SI-LIST] Virus Attachments? - Jon Powell
[SI-LIST] More On Viruses - Jon Powell
[SI-LIST] Re: More On Viruses - Bart Bouma
[SI-LIST] Re: Virus Attachments? - Mike LaBonte
[SI-LIST] Re: More On Viruses - webhugo-gcn
[SI-LIST] Re: Virus Attachments? - Tom Dagostino
[SI-LIST] Re: Report Creators - rlamoreaux
[SI-LIST] More on Viruses - e . sweetman
[SI-LIST] Re: Virus Attachments? - Peter Arnold
[SI-LIST] Re: Virus Attachments? - Ray Anderson
[SI-LIST] Re: More on Viruses - Grasso, Charles
[SI-LIST] Re: Virus Attachments? - Grasso, Charles
[SI-LIST] JOIN FOR FREE! LEARN and EARN! - Marlon Rafols
[SI-LIST] Fw: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce - Zhiping Yang
[SI-LIST] Re: JOIN FOR FREE! LEARN and EARN! - Ray Anderson
[SI-LIST] Re: Hspice simulator for board designs - Douglas Burns
[SI-LIST] FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce - Muranyi, Arpad
[SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce - Zhiping Yang
[SI-LIST] Job Opportunities at Optimal Corporation - Patrick Lam
[SI-LIST] Re: PCI Bus Routing - Ludvik
[SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce - Ege Engin
[SI-LIST] Re: PCI Bus Routing - MikonCons
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - istvan novak
[SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce - Wen Fred-Q16099
[SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce - herbert_lage
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - istvan novak
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce - Muranyi, Arpad
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Larry Smith
[SI-LIST] Agenda, IBIS Open Forum Summit at DesignCon East - Mirmak, Michael
[SI-LIST] Transient Analysis in Spectre - Parthasarathy Sampath
[SI-LIST] s2ibis - Jason Pritchard
[SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDD droop & Ground Bounce - Zhiping Yang
[SI-LIST] Looking for Job - BBabella11
[SI-LIST] Re: Looking for Job - BBabella11
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] ESD Calibration procedure - Moorthi
[SI-LIST] Sigrity seeks Regional Sales Account Manager - Teo Yatman
[SI-LIST] RMCEMC June 20th meeting reminder - Grasso, Charles
[SI-LIST] Image Conscious? - Sainath Nimmagadda
[SI-LIST] Re: Image Conscious? - Ray Anderson
[SI-LIST] Re: Image Conscious? - Sainath Nimmagadda
[SI-LIST] Developing High Speed Routing Rules - Harvey, Wilbur
[SI-LIST] Re: Developing High Speed Routing Rules - Hargin, Bill
[SI-LIST] Re: Developing High Speed Routing Rules - Chris Cheng
[SI-LIST] Re: Developing High Speed Routing Rules - Jon Powell
[SI-LIST] Re: Developing High Speed Routing Rules - Salkow, Steven
[SI-LIST] Issues WITH HPI Bus b/w ARM and TI DSP - sudarshan
[SI-LIST] PCB signal speed over temperature - hermann . ruckerbauer
[SI-LIST] Re: s2ibis - Mike LaBonte
[SI-LIST] pcb stackup - Peterson, James F (FL51)
[SI-LIST] Re: pcb stackup - Matthew Humphreys
[SI-LIST] Re: pcb stackup - mkhusid
[SI-LIST] Re: pcb stackup - Jon Powell
[SI-LIST] High Speed Soc Busses - manthos labropoulos
[SI-LIST] Re: pcb stackup - james . f . peterson
[SI-LIST] Re: Developing High Speed Routing Rules - Patrick Jabbaz
[SI-LIST] Re: pcb stackup - Alan Hilton-Nickel
[SI-LIST] Re: pcb stackup - npischl
[SI-LIST] Re: pcb stackup - Ron Matthews
[SI-LIST] clock tree at GHz range - lynda_liu123
[SI-LIST] Orcad layout to Allegro - Tim
[SI-LIST] Re: Orcad layout to Allegro - Jeremy W. Webb
[SI-LIST] How to fill copper? - wgf218
[SI-LIST] Reference plane - Felix Mbairi
[SI-LIST] srec2flash utility - Adeel Malik
[SI-LIST] Re: Orcad layout to Allegro - Painter, Chris
[SI-LIST] signal integrity seminar - June 26 -27, 2003 - Kathy Breda
[SI-LIST] Re: Reference plane - Loyer, Jeff
[SI-LIST] Presentations @ DesignCon EAST - Alyssa Starelli
[SI-LIST] Re: Presentations @ DesignCon EAST - Dima Smolyansky
[SI-LIST] Re: pcb stackup - Doug Brooks
[SI-LIST] Inductance extraction with FastHenry - manthos labropoulos
[SI-LIST] Re: pcb stackup - Virendra
[SI-LIST] Re: pcb stackup - Salkow, Steven
[SI-LIST] On-die decoupling MOS capacitor - Teh Lip Khoon
[SI-LIST] Re: On-die decoupling MOS capacitor - Raymond . Leung
[SI-LIST] AGP testing load - anshu . vij
[SI-LIST] On-die decoupling MOS capacitor - rajat . chauhan
[SI-LIST] si-list Digest V3 #171 - sunil-chandra . kasanyal
[SI-LIST] VNA Calibration - Zhangkun
[SI-LIST] Re: VNA Calibration - istvan novak
[SI-LIST] VNA/VSA question - hansm
[SI-LIST] Re: VNA/VSA question - Robert_Washburn
[SI-LIST] Re: pcb stackup - Doug Brooks
[SI-LIST] Re: pcb stackup - Lee Ritchey
[SI-LIST] Five emerging technologies that will revolutionize high speed systemspresentation at HCA mtg - Eric Bogatin
[SI-LIST] Effective Inductance - Moeller, Merrick
[SI-LIST] Re: pcb stackup - Lee Ritchey
[SI-LIST] Place and Route!!! - gk_raman
[SI-LIST] query. - ghori1
[SI-LIST] VISIT MY WEBSITE:http://www.geocities.com/ghori60/ghori.html - ghori1
[SI-LIST] Trace coating! - Pawel Rulikowski
[SI-LIST] Damped voltage oscillation - ueda
[SI-LIST] Re: Damped voltage oscillation - istvan novak
[SI-LIST] Re: Damped voltage oscillation - ueda
[SI-LIST] Re: Damped voltage oscillation - Zhangkun
[SI-LIST] Re: Damped voltage oscillation - istvan novak
[SI-LIST] Re: Five emerging technologies that will revolutionize high speed systems presentation at HCA mtg - Steven Ding
[SI-LIST] Re: Damped voltage oscillation - istvan novak
[SI-LIST] Re: Trace coating! - art_porter
[SI-LIST] High Speed SoC Bus - manthos labropoulos
[SI-LIST] VIA Capacity - Stradlin Donald
[SI-LIST] Re: VIA Capacity - Clewell, Craig
[SI-LIST] Re: VIA Capacity - art_porter
[SI-LIST] Re: FW: [IBIS-Users] Using IBIS models for VDDdroop & Ground Bounce - Abhijit Mahajan
[SI-LIST] Re: gtl signal ? - upainaik
[SI-LIST] Re: VIA Capacity - Hurst, Joe
[SI-LIST] Re: Damped voltage oscillation - Ingraham, Andrew
[SI-LIST] Re: VNA Calibration - D G
[SI-LIST] How to generate unloaded driver waveform - =?big5?b?Sm9obiBMaW4gKKpMtMK31yk=?=
[SI-LIST] Re: How to generate unloaded driver waveform - Jon Powell
[SI-LIST] Re: How to generate unloaded driver waveform (error correction) - Jon Powell
[SI-LIST] PCI input setup time question - marko.pulli
[SI-LIST] Re: PCI input setup time question - Jon Powell
[SI-LIST] Re: How to generate unloaded driver waveform - Beal, Weston
[SI-LIST] Re: VIA Capacity--> This Program was designed by Philli p Restall - Salkow, Steven
[SI-LIST] Re: VNA Calibration - istvan novak
[SI-LIST] Re: Damped voltage oscillation - istvan novak
[SI-LIST] Question on chassis ground - AAnbazhagan
[SI-LIST] RMCEMC June meeting available for download - Charles Grasso
[SI-LIST] Reducing SSO noise in an FPGA - Fabrizio Zanella
[SI-LIST] Eye display - Dorin
[SI-LIST] Re: Eye display - Peter Arnold
[SI-LIST] Re: Eye display - bpanos
[SI-LIST] Re: Eye display - Dorin
[SI-LIST] Re: Eye display - Ray Anderson
[SI-LIST] Re: Reducing SSO noise in an FPGA - Salkow, Steven
[SI-LIST] Re: Reducing SSO noise in an FPGA - Grasso, Charles
[SI-LIST] Re: Reducing SSO noise in an FPGA - Jerry Martinson
[SI-LIST] Re: Reducing SSO noise in an FPGA - Vinu Arumugham
[SI-LIST] Re: Reducing SSO noise in an FPGA - Juergen Flamm
[SI-LIST] Re: Reducing SSO noise in an FPGA - James . Freeman
[SI-LIST] Re: VIA Capacity--> This Program was designed by Ph illi p Restall -->Via_Current_spreadsheet_phillip_restall.xls - Salkow, Steven
[SI-LIST] Re: Reducing SSO noise in an FPGA - David Kaiser
[SI-LIST] Re: Reducing SSO noise in an FPGA - Zhangkun
[SI-LIST] Re: Reducing SSO noise in an FPGA - Michael Poimboeuf
[SI-LIST] Re: Reducing SSO noise in an FPGA - Zhangkun
[SI-LIST] Re: Flash with JTAG ISP - CJ Clark
[SI-LIST] Re: Reducing SSO noise in an FPGA - Salkow, Steven
[SI-LIST] Re: Reducing SSO noise in an FPGA - Michael Poimboeuf
[SI-LIST] Comaprison of hotstage(zuken) and hyperlynx - Manish Sharma
[SI-LIST] Re: Reducing SSO noise in an FPGA _ Capacitor ESL-values - Bart Bouma
[SI-LIST] Reducing SSO noise in an FPGA - Gregory R Edlund
[SI-LIST] Re: Reducing SSO noise in an FPGA - Perry Qu
[SI-LIST] Current Return Path - kfrobinson
[SI-LIST] Re: Current Return Path - Abhijit Mahajan
[SI-LIST] Re: Current Return Path - Loyer, Jeff
[SI-LIST] Re: Current Return Path - Ravinder . Ajmani
[SI-LIST] Re: Current Return Path - kfrobinson
[SI-LIST] Re: Current Return Path - kfrobinson
[SI-LIST] Re: Reducing SSO noise in an FPGA - Scott McMorrow
[SI-LIST] Re: Reducing SSO noise in an FPGA - Zhangkun
[SI-LIST] Re: Reducing SSO noise in an FPGA - istvan novak
[SI-LIST] Paper: Understanding the Importance of Signal Integrity - manthos labropoulos
[SI-LIST] Re: Paper: Understanding the Importance of Signal Integrity - Rich Peyton
[SI-LIST] Re: Reducing SSO noise in an FPGA - Fabrizio Zanella
[SI-LIST] Re: Paper: Understanding the Importance of Signal Integrity - art_porter
[SI-LIST] Re: Paper: Understanding the Importance of Signal Integrity - Ken Cantrell
[SI-LIST] via ? - Nimish Aggarwal
[SI-LIST] Re: Reducing SSO noise in an FPGA] - Scott McMorrow
[SI-LIST] Re: via ? - Martyn Gaudion
[SI-LIST] Re: via ? - Abe Riazi
[SI-LIST] Re: via ? - Lawrence Williams
[SI-LIST] Re: Paper: Understanding the Importance of Signal Integrity - Ray Anderson
[SI-LIST] Re: via ? - Dunbar, Tony
[SI-LIST] Re: Reducing SSO noise in an FPGA] - Chris Cheng
[SI-LIST] Re: via ? - webhugo-gcn
[SI-LIST] Re: Reducing SSO noise in an FPGA - bpanos
[SI-LIST] Re: Reducing SSO noise in an FPGA - Chris Cheng
[SI-LIST] I/O standard flexibility - Pushpraj Adhage
[SI-LIST] Re: Reducing SSO noise in an FPGA - stephanie . goedecke
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - boris . traa
[SI-LIST] cmic champion memory controller - karan bagga
[SI-LIST] Re: resend - Specctraquest model: mounted inductance - Bart Bouma
[SI-LIST] how to model an oscillator ? - Korcz, Cezary
[SI-LIST] Re: how to model an oscillator ? - Parthasarathy Sampath