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Thread Index for si-list, 06-2002

[si-list] || [06-2002 Date Index] [06-2002 Thread Index]

  1. [SI-LIST] Re: PCB Stackup, David Hoover
  2. [SI-LIST] Re: Errata Sheet for Wadell's "Transmission Line Design Handbook", Ken Beach
  3. [SI-LIST] I-V vs V-T endpoints In IBIS, Timothy Coyle
  4. [SI-LIST] New Errata Sheet for Wadell's "Transmission Line Design Handbook", Ray Anderson
  5. [SI-LIST] Re: PCB stack up, Senthil Selvam
  6. [SI-LIST] Re: I-V vs V-T endpoints In IBIS, Peters, Stephen
  7. [SI-LIST] commands:, Sanchez, Louis
  8. [SI-LIST] where can i find a book describe the details of the v-i and v-t curves, qzheng
  9. [SI-LIST] helical antenna for GPS, Glory.Tsai
  10. [SI-LIST] Re: Using W-element in HSPICE, Steve Corey
  11. [SI-LIST] Re: Decoupling capacitors, Larry Smith
  12. [SI-LIST] DDR SSTL-2 Signal Terminations, Anand . Kuriakose
  13. [SI-LIST] Com port, Alokby, Ahmed
  14. [SI-LIST] Re: Com port, Stephen Wu
  15. [SI-LIST] Decoupling of HSTL Vref, Aaron Frank
  16. [SI-LIST] SSTL-2 series termination in DDR Applications, Anand . Kuriakose
  17. [SI-LIST] Impedance of Interconnect, Bob Patel
  18. [SI-LIST] SMA connectors, Bob Patel
  19. [SI-LIST] PCIX A/D WIDTH Min, Brahim Koudssi
  20. [SI-LIST] Questions Concerning BGA Mounting, Paul Levin
  21. [SI-LIST] Re: Questions Concerning BGA Mounting, Anil Pannikkat
  22. [SI-LIST] Re: 2 kV Capacitor, gurunath vinayakrao kulkarni
  23. [SI-LIST] Job Oppotunities(EMI/EMC engineer, SAIT), kcnam
  24. [SI-LIST] IBIS conversion, Roger_Wu
  25. [SI-LIST] unsuscribe si-list, Miquel Roca Adrover
  26. [SI-LIST] Re: SSTL-2 series termination in DDR Applications, ANAND KURIAKOSE
  27. [SI-LIST] Re: (no subject), Umesh Painaik
  28. [SI-LIST], John Angulo
  29. [SI-LIST] SSTL-2 series terminations, Anand . Kuriakose
  30. [SI-LIST] Trace Width @ 3Gb/s, Rudy Sterner
  31. [SI-LIST] Re: Trace Width @ 3Gb/s, Rudy Sterner
  32. [SI-LIST] SI Position/Southern Cal, Fred Passmore
  33. [SI-LIST] Mutual inductance measurements of voltage drop, Douglas C. Smith
  34. [SI-LIST] Job opportunity, Michael Khusid
  35. [SI-LIST] [IBIS Model] Needed Consultant/Expert at generating IBIS models, Ron Nikel
  36. [SI-LIST] Hardware-Guru.com, Eitan k
  37. [SI-LIST] rs-485 reflection problem, Peterson, James F (FL51)
  38. [SI-LIST] Re: rs-485 reflection problem, Peterson, James F (FL51)
  39. [SI-LIST] 3dB or Knee Frequency, Anand . Kuriakose
  40. [SI-LIST] Re: 3dB or Knee Frequency, Ingraham, Andrew
  41. [SI-LIST] IBIS Packaging, Timothy Coyle
  42. [SI-LIST] Copper Fill, RayCaliendo
  43. [SI-LIST] SV: Re: Copper Fill --- correction, Anders Ekholm (ERA)
  44. [SI-LIST] Re: SV: Re: Copper Fill --- correction, Christman, Timothy (STP)
  45. [SI-LIST] SV: SV: Re: Copper Fill --- correction, Anders Ekholm (ERA)
  46. [SI-LIST] Re: Copper Fill, Loyer, Jeff W
  47. [SI-LIST] Re: Copper Fill --- correction, Ross Jatou
  48. [SI-LIST] PRBS Current Model, Shiming Wang
  49. [SI-LIST] SV: Re: SV: Re: Copper Fill --- correction, Anders Ekholm (ERA)
  50. [SI-LIST] a hspice w-element error, qzheng
  51. [SI-LIST] about split plane, Perry Qu
  52. [SI-LIST] Re: a hspice w-element error, Michael_Greim
  53. [SI-LIST] Re: : May 9th Presentation: "Radiation from Edge Effects in Printe..., Charles R. Patton
  54. [SI-LIST] hpsice question, qzheng
  55. [SI-LIST] Re: si-list Digest V2 #165, David Erikson
  56. [SI-LIST] Re: PCB Processing Comments, MikonCons
  57. [SI-LIST] Re: about split plane, George Tang
  58. [SI-LIST] IBIS model ramp option, John Ellis
  59. [SI-LIST] Re: IBIS model ramp option, Patrick_Carrier
  60. [SI-LIST] reference plane, evillaf
  61. [SI-LIST] Re: reference plane, Michael Nudelman
  62. [SI-LIST] Ghz/Gbs convert, joe nguyen
  63. [SI-LIST] Re: Ghz/Gbs convert, Gutzmann, Michael
  64. [SI-LIST] Allegro question., Kipnis, Oleg
  65. [SI-LIST] switching LVDS from loose to tight coupling, Robert Sefton
  66. [SI-LIST] Re: switching LVDS from loose to tight coupling, Michael Nudelman
  67. [SI-LIST] Re: Allegro question., Bill Dempsey
  68. [SI-LIST] Re: : May 9th Presentation: "Radiation from Edge Effects in Printe..., MikonCons
  69. [SI-LIST] TR0 to text/mathlab converter for HSPICE 2001.4, Yehuda Yizraeli
  70. [SI-LIST] decoupling capacitors, Juan Manuel
  71. [SI-LIST] Connexion FPGA-memory, Philippe Robert
  72. [SI-LIST] Re: TR0 to text/mathlab converter for HSPICE 2001.4, Ray Anderson
  73. [SI-LIST] Impedence of Differential Pair Not Over Plane, Ray Gordon
  74. [SI-LIST] Parasitic extraction and correlation to package delay measurement, Ross Jatou
  75. [SI-LIST] Re: Parasitic extraction and correlation to package delaymeasurement, Ozgur Misman
  76. [SI-LIST] Impedence of Differential Pair Not Over Plane (Revised), Ray Gordon
  77. [SI-LIST] Asymmetric Coupled Stripline, Ken Taylor
  78. [SI-LIST] Decoupling of diff pair devices, Steeve Gaudreault
  79. [SI-LIST] Re: Asymmetric Coupled Stripline, Ray Anderson
  80. [SI-LIST] modelling of wire as w-element transmission line, Jayanta Choudhury
  81. [SI-LIST] Odd mode impedance, Mir Faiz
  82. [SI-LIST] Re: modelling of wire as w-element transmission line, Ray Anderson
  83. [SI-LIST] Re: Odd mode impedance, Ray Anderson
  84. [SI-LIST] connectors, Juan Manuel
  85. [SI-LIST] Re: connectors, Clewell, Craig
  86. [SI-LIST] Re: Decoupling of diff pair devices, Michael Khusid
  87. [SI-LIST] S-I Candidates, Mahesh Grossman
  88. [SI-LIST] High Speed Design Class from UC Berkeley, Ritchey Lee
  89. [SI-LIST] Re: [SI-LIST]modelling of wire as w element transmission line, Jayanta Choudhury
  90. [SI-LIST] Post Layout Signal Integrity Analysis, Scuba Snail
  91. [SI-LIST] Re: Post Layout Signal Integrity Analysis, McKinley, Jory D
  92. [SI-LIST] modelling of wires as w-element transmission line, Jayanta Choudhury
  93. [SI-LIST] modelling of wire using w-element transmission line, Jayanta Choudhury
  94. [SI-LIST] Hi all, Kedar P. Apte
  95. [SI-LIST] AC Termination Question, Doug Brooks
  96. [SI-LIST] Re: AC Termination Question, Moran, Brian P
  97. [SI-LIST] Power filtering, Martin Euredjian
  98. [SI-LIST] Signal Integrity Manager needed, Santa Clara, CA;, Mark Apton
  99. [SI-LIST] Signal Integrity Manager needed, Santa Clara, CA - [NVIDIA], Joshua Hasten
  100. [SI-LIST] Post Layout - Thank you so much, Scuba Snail
  101. [SI-LIST] SI Tools, Ingo Kupper
  102. [SI-LIST] how to decouple this chip (mux and demux ), qzheng
  103. [SI-LIST] {SI-LIST] help SGMII, s.raja
  104. [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara, CA;, Clewell, Craig
  105. [SI-LIST] Berkeley SPICE buffer models?, Mike Mayer
  106. [SI-LIST] Re: SI Tools, CCT20ES
  107. [SI-LIST] Re: Signal Integrity Manager needed, Santa Clara,C A;, Aubrey_Sparkman
  108. [SI-LIST] Re: Power filtering, Lewandowski, Bob
  109. [SI-LIST] Re: Book, Bill Hargin
  110. [SI-LIST] IBIS VT & VI curve verification, Lin Wee



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