FreeLists / si-list / [SI-LIST] Re: Trace Width @ 3Gb/s

[Scott McMorrow <scott@xxxxxxxxxxxxx>]

Rudy,

I calculate a conductor loss of  about 0.15 dB/inch.

At 1.5625 GHz dielectric loss is 0.10 db/inch with a loss tangent of 0.014
Or 0.21 db/inch with a loss tangent of 0.030

So the worst case total trace loss per inch is:

0.25 dB/in @ 0.014 loss tangent
0.36 dB/in @ 0.030 loss tangent

for 10 inches of trace the total loss would be:


2.5 dB @ 0.014 loss tangent
3.6 dB @ 0.030 loss tangent

So, even at a loss tangent of 0.030 (which is quite high) your signal 
amplitude has been degraded by only 34%, which is not very significant.

I would look somewhere else for your problem.  On the board the most 
likely possibilites are the via transitions from the traces to the 
connectors, or from the package to the traces. You might also have set 
up a resonance due to some mismatch in the system, or you may have a 
poorly designed package with excessivel loss at 3 Gbps.

Good luck in hunting down your problem.


Regards,

Scott


-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com



Rudy Sterner wrote:

>Hello,
>
>   The error occurs in the following type of pattern:  '0001010'.
>It is at the first '1'.  The signal is NRZ.  We observed it on
>the scope and noticed that the pulse resulting from the
>first '010' transitions was smaller than the second pulse which
>explains the error.
>
>  As for the dimensions:  We buried the traces between two
>ground planes.  We used 4-mil width, 7-mil spacing, half-oz.
>copper.  Distance from trace to ground plane is 5 mils.  The
>signals are AC coupled.  The individual trace impedance is
>higher than 50 Ohms; however we control both the driver
>and receiver impedance.  Neither seemed to help in this case.
>
>  For the next round, we are going to run these traces on the outer
>layer to minimize the effects of vias.
>
>Regards
>
>
>Rudy Sterner
>
>
>----- Original Message -----
>From: "Hassan O. Ali" <hassan@xxxxxxxx>
>To: "Rudy Sterner" <rsterner@xxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>Sent: Monday, June 10, 2002 9:00 AM
>Subject: Re: [SI-LIST] Trace Width @ 3Gb/s
>
>
>  
>
>>Rudy,
>>
>>Could you be specific on the kind of issues you have with the SerDes link?
>>    
>>
>That way you
>  
>
>>can receive suggestions that are more specific to your situation.
>>
>>Yes, 4-mil tracks can be a problem. With those tracks, in a microstrip
>>    
>>
>format you need
>  
>
>>less than 3-mil height to achieve close to 50-ohm single-ended line
>>    
>>
>impedance (which
>  
>
>>might be your goal). With that small height and at that data rate,
>>    
>>
>component pads
>  
>
>>(especially AC-coupling cap pads, if you have any) start to dominate
>>    
>>
>heavily causing
>  
>
>>tremendous impedance discontinuities.
>>
>>In addition, narrow tracks give rise to higher loss - both line-loss and
>>    
>>
>reflection loss
>  
>
>>due to pronounced discontinuities at various locations (the connector
>>    
>>
>launch-point is
>  
>
>>one of the most important ones).
>>
>>Regards.
>>
>>Hassan.
>>
>>
>>
>>
>>
>>On Jun 10, "Rudy Sterner" <rsterner@xxxxxxxx> wrote:
>>    
>>
>>>Hello,
>>>
>>>   We have some issues with a SerDes which we think
>>>may be related to the trace width on the serial line.  The
>>>serial  port is a differential pair passing data at 3 Gb/s.
>>>The trace width is 4 mils.  Length is approximately 5 inches.
>>>The differential impedance is 100 Ohms.  Other information
>>>which may be of use is the board material is FR-4 with an
>>>Er of 3.9.  It is specified at this data rate.
>>>
>>>  My question is:  Are the traces too narrow?  Should I
>>>expect better performance with 8-mil traces?
>>>
>>>Thank You
>>>
>>>Rudy Sterner
>>>LSI Logic
>>>
>>>      
>>>
>>    
>>
>
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-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com




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