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[SI-LIST] Re: Trace Width @ 3Gb/s

  • From: "Hassan O. Ali" <hassan@xxxxxxxx>
  • To: "Rudy Sterner" <rsterner@xxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 10 Jun 2002 12:00:31 -0400 (EDT)
Rudy,

Could you be specific on the kind of issues you have with the SerDes link? That 
way you 
can receive suggestions that are more specific to your situation.

Yes, 4-mil tracks can be a problem. With those tracks, in a microstrip format 
you need 
less than 3-mil height to achieve close to 50-ohm single-ended line impedance 
(which 
might be your goal). With that small height and at that data rate, component 
pads 
(especially AC-coupling cap pads, if you have any) start to dominate heavily 
causing 
tremendous impedance discontinuities. 

In addition, narrow tracks give rise to higher loss - both line-loss and 
reflection loss 
due to pronounced discontinuities at various locations (the connector 
launch-point is 
one of the most important ones).

Regards.

Hassan.





On Jun 10, "Rudy Sterner" <rsterner@xxxxxxxx> wrote:
> 
> Hello,
> 
>    We have some issues with a SerDes which we think
> may be related to the trace width on the serial line.  The
> serial  port is a differential pair passing data at 3 Gb/s.
> The trace width is 4 mils.  Length is approximately 5 inches.
> The differential impedance is 100 Ohms.  Other information
> which may be of use is the board material is FR-4 with an
> Er of 3.9.  It is specified at this data rate.
> 
>   My question is:  Are the traces too narrow?  Should I
> expect better performance with 8-mil traces?
> 
> Thank You
> 
> Rudy Sterner
> LSI Logic
> 

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