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[SI-LIST] Impedance of Interconnect

  • From: Bob Patel <whizplayer@xxxxxxxxx>
  • To: si_list <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 6 Jun 2002 09:26:50 -0700 (PDT)
Hi! I had couple of questions on designing an
interconnect with two daughter cards and a mother
board.
Given that his interconnect has two work reliabily
upto 8GHz i.e. accounting for the harmonics due to the
fast risetimes and this interconnect has ac coupling
in the path.
Now, if the desired impedance of the interconnect is
to be 100ohm differential then the use of AC coupling
lowers the impedance of the interconnect.
Now, I know of couple of ways to attack this:
1)Increase the impedance gradually as you arrive the
pad of the capacitor & in that way counter the dip in
impedance due to the capacitor.
2) I have removed plane underneath the pads of the
capacitor to lower the C due to the pads.

Are there any other methods of designing an
interconnectwith impedance maintained around +/-10% of
100ohms.
Any input appreciated.
Thanks
Bob

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