FreeLists / si-list / [SI-LIST] Re: Decoupling capacitors

[Larry Smith <Larry.Smith@xxxxxxx>]

Mike - For SI purposes, there is not much you can do at the PCB level
to help the PDS impedance above the package corner frequency.  However,
there may (probably will) be EMI reasons to use capacitors on the core
power planes to knock down emissions at higher frequencies.

We use 3 capacitors per decade to make the PDS impedance sufficiently
flat.  The fifteen values of ceramic X5R/X7R capacitors that we most
commonly use are:

        100uF   47uF    22uF
         10uF   4.7uF   2.2uF
          1uF   470nF   220nF
        100nF   47nF    22nF
         10nF   4.7nF   2.2nF

This menu is usually sufficient for SI caps.  We mount these caps on
pads that are much less than 1nH so the series resonant frequencies
(SRF) range from 360kHz to 150 MHz.  Five decades of capacitance value
covers about 2.5 decades of frequecy because the SRF goes as the square
root of capacitance.  The ESR's range from 2 mOhms to 300 mOhms, with
the lower valued caps having the highest ESR.  1uF and below is
available in 0603 case sizes.  100uF caps are now available in 1812
size.

Our power planes generally have more than 10 nF capacitance.  The ESR
of the capacitors below 10nF is so high that many, many capacitors are
required in parallel to reach target impedance.  It is best to use
power plane capacitance above about 100 MHz rather than try to do it
with discretes.  There may be a few well defined EMI frequencies that
you want to attack with carefully chosen high quality capacitors, but
that is a different issue.

regards,
Larry Smith
Sun Microsystems 

> From: "Brown, Mike (AUS)" <mibrown@xxxxxx>
> To: <Larry.Smith@xxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> <snip>
> 
> range.  Individual capacitors have an impedance vs frequency profile
> that look like a "V".  By selecting the optimum number of capacitors
> with different values, it is possible to combine a lot of these "V's"
> together to approach a flat curve over a broad frequency range.  That
> essentially presents a resistance to the load over the frequency
> range.
> 
> <snip>
> = = = = =
> Larry,
> 
> It would appear that I don't have to worry about board impedance above the
> package corner frequency, where the package X exceeds the target impedance.
> I may need a bunch of different cap values and resonances to keep the board
> and PDS impedance flat up to that frequency, however.
> 
> What is an acceptable spacing between the series-resonant "V's" to avoid
> unacceptably high parallel resonance impedance peaks?  1 per decade?  1 per
> octave?
> 
> I know, I know.  "It Depends."  On what?
> 
> 
> Thanks
> 
> Mike
> 

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