FreeLists / si-list / [SI-LIST] Inductance of Via

["Yibing Tang" <ytang@xxxxxxxxxxxxxxxxx>]

Hi, all,
I use a formula to calculate the inductance of through hole via,
L=5.08h[ln(4h/d)+1]
However, I find that it is not suitable for small ratio of h to d. From this
formula,if decrease the ratio, I could get very lower inductance, even
negative.
My question is how far I can go to low the inductance.
Any comments are appreciated,

Yibing Tang
ytang@xxxxxxxxxxxxxxxxx

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of D. C. Sessions
Sent: Friday, June 08, 2001 11:07 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SSTL_3 output buffer design


On Friday 08 June 2001 01:39, rajat.chauhan@xxxxxx wrote:
> Hello SI list,
>   I have a question related to SSTL_3 (class I or class II)ouput buffer
> designing.I have already designed output buffers for LVTTL and LVCMOS
> specifications and my question is:
>
> 1. Is the designing of SSTL_3 ouput buffer is exactly same as that of
>  LVTTL or LVCMOS output buffers (keeping Voh/Ioh & Vol/Iol values
> according to SSTL_3 specs) ?

Nope.

> 2. If not, what are the extra related issues which i have to look for?

Since SSTL in general is shunt-terminated, you get quite a bit of your
launch wave from the turnOFF of the previously-on driver transistor.
(e.g., rising-edge wave from NMOS turnoff.)  So it's important to be
careful to choreograph the turnoff/turnon process much more carefully
than you do with unterminated CMOS.

Secondly, since a fair bit of your timing budget lies in the difference
between rising and falling delay, you need to watch the skew between
them rather than just the maximum of the two.

Third, you have to watch the crosspoint.  This is partly related to the
rise/fall skew business, but not identical.

It also helps to keep an eye on the output _impedance_, not just drive
operating points.  In an SSTL environment the driver is going to have
to eat a lot of small reflections when it's not in the steady-state
condition.

> 3. Is there any standard test load(test enviorment) for testing,
> specifying delays and specifying max. freq. of the designed buffer.

We have a rule in JC-16 that anyone who says "test load" buys beer
for the committee.  We are pretty careful to talk about "characterization
load" instead.  And for that purpose, have a look at JESD8-9A (the
revised SSTL-2 spec).  I'm afraid that there hasn't been much maintainence
on SSTL-3 simply because we're not aware of anyone using it.

D. C. Sessions
Chair, JEDEC JC-16

--
| The race is not always to the swift, nor the battle to the strong. |
| Because the slow, feeble old codgers like me cheat.                |
+--------------- D. C. Sessions <dcs@xxxxxxxxxxxxxxxx> --------------+
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