FreeLists / si-list / [SI-LIST] R: Reply: Antwort: Re: Decoupling capacitors for BGA

[<gianguida@xxxxxxxx>]

Hi Folks,
once again I beleive that the problem of capacitor placement and values 
selection,
take in account all inductance, study plane resonaces...
is very well suited for simulation approach...
there are simply too many think to take in to account to solve the problem with 
a simple formula 
and there are several specialized simulators oin the market to not consider the 
possibility to perform simulation 
to get guideline to be used in our own design


Giancarlo



-----Messaggio originale-----
Da: si-list-bounce@xxxxxxxxxxxxx per conto di ???
Inviato: lun 15/05/2006 17.33
A: andreas lenkisch; dagmara.avanindra@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx; 
subramanian1683@xxxxxxxxx
Oggetto: [SI-LIST] Reply: Antwort: Re: Decoupling  capacitors for BGA
 
 
 
Hi all,
 
   Decoupling  for BGA is a important topic, especially for the core power net 
in which there 
 
are so many capacitors. Because the location of decoupling capacitors are 
required as 
 
possible as close to the device in the IC's datasheet , what's more, there are 
very little 
 
areas for placement.
 
   There are tow way for this question, one hand is using smaller package, such 
as 0402,0201; 
 
the other hand is place cap around IC; As my experence,the first method is more 
easier, 
 
usually, take sure that one cap per tow or three pins.but for the second 
method, it is 
 
difficult for the larger loop inductance. but I think it is very imposible, its 
essence is 
 
how large the cap's parasitic inductance is. As long as the loop inductance is 
enough small,
 
the method is feasible.How to calculate the loop inductance? 
 
    exept for simulation soft, can we get a simple formula to evaluate it?
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