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[SI-LIST] Re: 8B10B encode/decode
- From: Yafei Bi <yafei_bi@xxxxxxxxx>
- To: yafei_bi@xxxxxxxxx, steve weir <weirsi@xxxxxxxxxx>, si-list@xxxxxxxxxxxxx
- Date: Thu, 11 May 2006 12:04:42 -0700 (PDT)
Hi, Steve,
What is 2b/1b encoding, can you explain.
Thanks
Yafei
--- Yafei Bi <yafei_bi@xxxxxxxxx> wrote:
> Steve, thanks.
>
> the implementation target is ASIC and I am very
> limited on the silicon area.
>
> Thanks
>
> Yafei
>
> --- steve weir <weirsi@xxxxxxxxxx> wrote:
>
> > It depends on the implementation target, ASIC,
> FPGA
> > etc. That's a
> > better question for the language or FPGA
> reflectors.
> > There are lots
> > of encoder / decoders for sale.
> >
> > 2b/1b takes few gates, but lots of wires.
> >
> > Steve
> >
> > At 11:36 AM 5/11/2006, Yafei Bi wrote:
> > >Hi, SI experts,
> > >
> > >Can someone explains to me how 8B10B
> > encoding/decoding
> > >can be implemented with minimum hardware?
> > >
> > >I am aware of the concept but don't know much
> about
> > >the details to figure out how much hardware(in
> this
> > >case, silicon area) is needed to implemented the
> > >functions.
> > >
> > >Arew there any other ways to encode the data
> stream
> > to
> > >ensure DC balance, and requires very few gates?
> > >
> > >any suggestion/web links are appreciated.
> > >
> > >Thanks
> > >
> > >Yafei Bi
> > >
> > >
> >
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