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[SI-LIST] Re: how to extract RLC values for package
- From: "Yu Wang" <Yu.Wang@xxxxxxxxxxxx>
- To: <prathibha@xxxxxxxxxxxxxxx>, "SI-List" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 10 May 2006 12:56:55 +0900
HSPICE can support different package type as defined in ICM spec.=20
You do not need to have the lumped value of R/L/C.
Regards.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Lynne D. Green
Sent: 2006=C4=EA5=D4=C27=C8=D5 2:19
To: prathibha@xxxxxxxxxxxxxxx; 'SI-List'
Subject: [SI-LIST] Re: how to extract RLC values for package
Hello, Prathibha,
Are you perhaps planning to create an IBIS pkg model? It sounds like =
you have the data to do that.
If you use a pkg model, it replaces the parameters R_pkg, L_pkg, and =
C_pkg.
In that case, the "*_pkg" subparameters could be:
R_pkg =3D the sum of resistances for a typical pin L_pkg =3D the sum of =
inductances for a typical pin + bondwire inductance (if
any)
C_pkg =3D the sum of capacitances for a typical pin
Some tools might allow an ICM model for the package model (replacing the =
"*_pkg" subparameters. You would need to talk to the EDA tool vendors =
about details.
Best regards,
Lynne
"IBIS training when you need it, where you need it."
Dr. Lynne Green
Green Streak Programs
http://www.greenstreakprograms.com
425-788-0412
lgreen22@xxxxxxxxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Prathibha
Sent: Friday, May 05, 2006 3:56 AM
To: SI-List
Subject: [SI-LIST] how to extract RLC values for package
Hi Gurus ,
How can we get the RLC values for a package ?. We have extracted =
package model, but could not get a combined RLC values . We are using =
APD for designing the package .
Please advise .
Thanks and Regards,
Prathibha
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Istvan Novak
Sent: Thursday, May 04, 2006 6:40 PM
To: GStokes@xxxxxxxxx
Cc: SI-List
Subject: [SI-LIST] Re: Routing Signals Between PWB Layers - Part 2
Geoff, Doug,
This example nicely shows the importance of proper power distribution =
design.
The emission peaks correspond to the modal resonances of the PCB planes.
As Doug points out in the article, moving the planes closer would reduce =
the emission about proportionally. However, if one wants to stay with a =
four-layer construction, reducing the plane separation is not a viable
solution: it would either result in an unmanageably thin board, or if we =
add the tickhness back to the top/bottom dielectrics, in a dramatically =
reduced routing density.
Nearby grounding vias would help, but in practical cases the two planes =
are at different DC potentials, so it must be a bypass capacitor rather =
than a stitching via. A single bypass capacitor will do little in the =
hundreds of MHz frequency range, even if it serves only one signal. =
Also, if we have wide busses instead of a single trace, trying to =
provide a return path locally to all of the layer transitions becomes =
much harder to implement.
A more realistic and straightforward solution is to design the =
power-distribution network in such a way that it does not exhibit large =
resonances. In multi-layer boards, where we may also have ground-ground =
planes creating such cavities, the solution is stitching vias, but not =
necessarily near the layer transitions. We would just need to make sure =
that the large resonating cavity is broken up to sufficiently small =
blocks such that the lowest resonance frequency is safely above the =
highest frequency of excitation.
Regards,
Istvan Novak
SUN Microsystems
Geoff Stokes wrote:
>Hi Doug
>
>In this experiment, you appear to have no plane vias adjacent to the=20
>signal vias. What would happen if a few plane vias were added around=20
>the transitions and fairly close by?
>
>Geoff Stokes
>Systems Engineer
>Zetex Semiconductors plc
>Zetex Technology Park
>Chadderton
>Oldham
>OL9 9LL
>UK
>=3D20
>+44-161-622-4857
>www.zetex.com
>www.zetex.cn
>=3D20
>
>=3D20
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Doug Smith
>Sent: 03 May 2006 21:41
>To: SI-List
>Subject: [SI-LIST] Routing Signals Between PWB Layers - Part 2
>
>Hi All,
>
>I have been writing and recording again and have posted part 2 of =
my=3D20=20
>article on signals that change layers in a PWB.
>
>Abstract: Printed wiring board, PWB, signal paths must often =
change=3D20=20
>layers in a board stackup. Under some conditions this can cause=3D20=20
>problems. An emissions example is used to illustrate the =
conditions=3D20=20
>where changing layers can cause problems.
>
>The link to the article is the picture of the emissions plot at =
the=3D20=20
>bottom of the home page at http://emcesd.com .
>
>There is also an audio discussion of this article on my podcast=20
>site:=3D20 http://emcesd-podcast.com where the direct link to the =
article is:
>
>http://emcesd-podcast.com/2006/may/2006-0503.mp3
>
>Can't download mp3 files? Download the following instead:
>
>http://emcesd-podcast.com/2006/may/2006-0503.dcs
>
>After download, change the extension from .dcs to .mp3 and the =
file=3D20=20
>will then be able to play on most computers. Since the last HFNews=3D20 =
>there have been two new podcasts posted.
>
>Doug
>--=3D20
>-------------------------------------------------------
> ___ _ Doug Smith
> \ / ) P.O. Box 1457
> =3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D Los =
Gatos, CA 95031-1457
> _ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
> / /\ \ ] / /\ \ Mobile: 408-858-4528
>| q-----( ) | o | Email: doug@xxxxxxxxxx
> \ _ / ] \ _ / Website: http://www.dsmith.org
>-------------------------------------------------------
>
>
>
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