FreeLists / si-list / [SI-LIST] Re: FPGA SI Issues in Space Applications

["liz_m_mooney" <liz_m_mooney@xxxxxxxxx>]

Hi Sammit,

This is my first time posting to the list and I just wanted to add a 
couple of things that I have learned about designing for space 
applications.

First of all, there are several different ways that a part in space 
can be affected by radiation including SEU, SEU latchup, high 
radiation doses over a short period of time, and low radiation doses 
over a long period of time.  Just because a part can handle MRads of 
radiation at once doesnt neccessarily mean it can withstand lower 
radiation levels over a 7 year mission.  

What makes a part RADHard is the different type of doping materials 
used in the part.  Some materials can withstand more radiation than 
others but because the manufacturing process is just different and 
produces less parts from the die, its more expensive. Not only that, 
some designs (FPGA specific) are actually slower but they are bullet 
proof.

Some of the things that you can use in your design:
1.  Design triple modular code.  This can usually be done by a 
setting in the design software you are using, compiler setup, or you 
can just do it yourself.  If you let the tool do it for you, it will 
make everything redundant including things like "or" gates which 
arent a big deal, but a flip flop is.  So if you design the 
redundancy yourself, your code will take up less space.

2.  Implement a WDT in the code. This will force the code to 
constantly be doing something.

3.  Use redundancy: have two FPGAs on the card.

4.  Implement a current monitor on the part. If you see a spike in 
current you know that the part has been hit with some radiation and 
you can switch to your redundant part fast. Along with this, make 
sure to use a fuse for your power switching so no other parts will 
be damaged.

5.  Put a good amount (.25 inch thick) of aluminum or steel around 
the part. 

I hope this helps,

Liz Mooney




--- In si-list@xxxxxxxxxxxxxxx, austin.lesea@... wrote:
>
> > Hi,
> > 
> > My first time posting here.  Let me know if this is useful, or 
not.
> > 
> > 1.  Maxwell's equations work the same in a vacuum as in air, so 
all SI 
> > design for space is the same as for on earth here.  Just need to 
> > remember that in space, temperatures might vary (a lot, or not, 
thermal 
> > design is a challenge when there is no air to carry heat away) 
so 
> > simulating fast/cold, and weak/hot corners is required (same as 
in any 
> > earth based design - just make sure you simulate the right 
temperatures!).
> > 
> > 2.  Accumulating total radiation dose in space means that the 
voltage 
> > thresholds of the transistors will shift.  After a very long 
time, that 
> > may affect operation.  One trick is that you may configure the 
device as 
> > a giant shift register, clock it a few hundred MHz, and cook the 
part 
> > for 24 to 72 hours and bake out the trapped ions (to a very 
large 
> > extent).  This trick can be done after you see the current 
increasing 
> > for the core after a few years, or tens of years (if the mission 
lasts 
> > that long).  One more benefit of using a FPGA for space.
> > 
> > 3.  Heavy ions in space cause latchup in bulk CMOS, so that is 
why we 
> > have the Xilinx QPRO series which uses epitaxial wafers.  Do not 
use 
> > CPLDs as they are not made in epitaxial process and no one knows 
what 
> > heavy ions do to the EEPROM cells.  If you wish to use a 
commercial FPGA 
> > device, make sure you can turn it off, and turn it back on after 
each 
> > latchup (so it won't turn to toast).
> > 
> > 4.  Designing for SEUs in space is totally different than even 
for 
> > airplanes at 40,000 feet:  a iron or gold ion at near the speed 
of light 
> > carries a lot more punch that a puny neutron or proton in the 
earth's 
> > atmosphere (which is all you can get).  The energy that smacks a 
chip 
> > with a heavy ion can do some serious flipping, and transients, 
and 
> > possibly damage.  It takes a whole different approach (full TMR, 
> > duplicate units, and so on).  Here on earth or even in the 
stratosphere, 
> > there are alternate techniques that are just fine.
> > 
> > Happy to answer questions about satellites, and design for space.
> > 
> > Austin Lesea, IC Design, APD Division (Virtex line), Xilinx, San 
Jose
> > 
> > 
> > 
> > 
> >  > To: si-list@...
> >  > Subject: [SI-LIST] Re: FPGA SI Issues in Space Applications
> >  >
> >  > Assuming you are talking about satellites and not launchers, 
one issue
> >  > to consider is that long term radiation affects transister
> >  > characteristics. So you can't trust specs such as Vil, Vih, 
Vol, Voh,
> >  > rise times, propogation delays.
> >  >
> >  > So how do you design? You understand what the affects are, 
and you
> >  > adjust the numbers for the worst case over the lifetime of the
> >  > satellite. Lots of extra margin in the design is highly 
recommended.
> >  >
> >  > I'm glad to see that you've addressed the SEU issue. A flip-
flop that
> >  > decides to change state randomly is difficult to design 
around. It is
> >  > even harder when the flip-flop is controlling the 
configuration of the
> >  > FPGA. How are you dealing with radiation induced latch-up?
> >  >
> >  > Using non-radiation hardened electronics in space is tricky.
> >  > There was once a Japanese satellite that used seven 
microprocessors.
> > 
> > 
> > The
> > 
> >  > processors were not radiation hardened, but they didn't worry 
because
> > 
> > 
> > of
> > 
> >  > all of the redundancy. If one or two get a radiation hit, the 
others
> >  > take over and reset the crashed cpus. Then along came a 
strong solar
> >  > flare and knocked out all seven at once. End of satellite.
> >  >
> >  >    -tom
> >  >
> >  > -----Original Message-----
> >  > From: si-list-bounce@...
> > 
> > 
> > [mailto:si-list-bounce@...]
> > 
> >  > On Behalf Of Sammit Adhya
> >  > Sent: Tuesday, April 25, 2006 11:21 PM
> >  > To: si-list@...
> >  > Subject: [SI-LIST] FPGA SI Issues in Space Applications
> >  >
> >  >
> >  > Hello All,
> >  >
> >  > This is my first time posting to the list so hopefully the 
question
> >  > isn't too generic. I'm currently working on a research 
project to use
> >  > FPGAs as flight computers in space at the University of 
Colorado. I
> > 
> > 
> > was
> > 
> >  > wondering if people had any general advice for designing 
circuits in
> >  > space with it comes to signal integrity and high radiation
> > 
> > 
> > environments.
> > 
> >  > Things like single event upsets have already been addressed, 
but I was
> >  > looking for some insight issues beyond SEUs, SETs and SEEs. 
Any
> > 
> > 
> > specific
> > 
> >  > ways of routing circuits or designing them to inherently 
protect them
> >  > the harsh space environment? Thanks!
> >  >
> >  > --
> >  > Sincerely,
> >  > Sammit Adhya
> > 
> 
> 
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