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Thread Index for si-list, 05-2005

[si-list] || [05-2005 Date Index] [05-2005 Thread Index]

  1. [SI-LIST] volume resistivity (or conductivity) of printed circuit boards, jan . vercammen1
  2. [SI-LIST] Re: volume resistivity (or conductivity) of printed circuit boards, Dimiter Popoff
  3. [SI-LIST] chapter 1 of Signal Integrity Simplified as pdf on web site, Eric Bogatin
  4. [SI-LIST] Question about Academics, Silqun Leung
  5. [SI-LIST] Re: chapter 1 of Signal Integrity Simplified as pdf on web site, Ray Anderson
  6. [SI-LIST] Re: Finding the impedance of a PCB trace, Doug Brooks
  7. [SI-LIST] Re: Need advice on basic 6-layer stackup, Graham Davies
  8. [SI-LIST] Re: Finding the impedance of a PCB trace - Ansoft/P olar, Grasso, Charles
  9. [SI-LIST] 1000BASE-SX, Santangelo, Steven
  10. [SI-LIST] Re: 1000BASE-SX, steve weir
  11. [SI-LIST] power plane question, ma mu
  12. [SI-LIST] Out of Office AutoReply:, Juergen Flamm
  13. [SI-LIST] verification of current measurements, Doug Smith
  14. [SI-LIST] [Fwd: [IBIS-Users] IBIS Summit First Call of Papers - DAC June14th, 2005, Anaheim CA], Syed Huq
  15. [SI-LIST] doubt in pci interface, smitha.anand
  16. [SI-LIST] Re: doubt in pci interface, steve weir
  17. [SI-LIST] RC time constant question, nagaraj
  18. [SI-LIST] Passivity of an Inductance Matrix, Jones Edward
  19. [SI-LIST] Broadside coupled line vertical registration, Mark Burford
  20. [SI-LIST] Re: Broadside coupled line vertical registration, Ed Sayre III
  21. [SI-LIST] Maximum length of 1000basetT diff pair traces from PHYs to magnet ics, Aleksandr Oysgelt
  22. [SI-LIST] Curved vs. 90 degree PCB trace paper, Chris McGrath
  23. [SI-LIST] Re: Curved vs. 90 degree PCB trace paper, Hargin, Bill
  24. [SI-LIST] Re: RC time constant question, Raymond . Leung
  25. [SI-LIST] Comments on "Do you really ship products at BER 10e-xx ?", Mike Williams
  26. [SI-LIST] Re: Maximum length of 1000basetT diff pair traces from PHYs to magnet ics, Murphy Jack-MGI2488
  27. [SI-LIST] Probe headers on DDR SDRAM, Devendra Singh Rana
  28. [SI-LIST] Experimental/Prototype Supplies, Jim Antonellis
  29. [SI-LIST] JEDEC 1.8V HSTL Interface, murali.repal
  30. [SI-LIST] Metal Fills?, manish khemani
  31. [SI-LIST] Re: Metal Fills?, Christopher.Jakubiec
  32. [SI-LIST] PI Analysis about Core Power Supply, Zhangkun
  33. [SI-LIST] Re: PI Analysis about Core Power Supply, Yafei Bi
  34. [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?", Chris Cheng
  35. [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?", Grasso, Charles
  36. [SI-LIST] Re: Comments on "Do you really ship products at BER 10e -xx ?", Chris Cheng
  37. [SI-LIST] DDR2 unbuffered DIMM specification?, Bob Perlman
  38. [SI-LIST] Re: DDR2 unbuffered DIMM specification?, Bob Perlman
  39. [SI-LIST] RMCEMC Presentation download available, Grasso, Charles
  40. [SI-LIST] IEEE-EMCS SCV Chapter meeting on Tuesday May 10, 2005, Ahmad Fallah
  41. [SI-LIST] Apple Needs Good SI People, Jay Fischer
  42. [SI-LIST] ground conductors on TNT, gustavo . duenas
  43. [SI-LIST] Re: ground conductors on TNT, Ray Anderson
  44. [SI-LIST] SI position in Sunnyvale, CA, Yishai Kagan
  45. [SI-LIST] Discontinuities on PCB, Charles Harrington
  46. [SI-LIST] Re: Discontinuities on PCB, Mark Burford
  47. [SI-LIST] hfss 9.2, Kamran Azizi
  48. [SI-LIST] Estimate ISI with S parameters?, John Lin (林朝煌)
  49. [SI-LIST] reg VOIP, Prakash N
  50. [SI-LIST] The function of VBW in spectrum analyzer, Zhangkun
  51. [SI-LIST] 20%-80% rise time, nagaraj
  52. [SI-LIST] Re: The function of VBW in spectrum analyzer, Ray Anderson
  53. [SI-LIST] Voids in BGA joints, Sol Tatlow
  54. [SI-LIST] Re: Estimate ISI with S parameters?, Ray Anderson
  55. [SI-LIST] Re: hfss 9.2, Ming Tsai
  56. [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ?, ma mu
  57. [SI-LIST] Re: difference between two batches of main boards?, Abraham Peng
  58. [SI-LIST] Re: How can I simulate the influence of power plane noise on the signal trace ?, steve weir
  59. [SI-LIST] Do i have to use microstrip lines?, ray jiang
  60. [SI-LIST] Decoupling capacitors, Joe Paul M
  61. [SI-LIST] Routing 10G differential lines over Standard FR-4, sunil.mekad
  62. [SI-LIST] Re: Routing 10G differential lines over Standard FR-4, steve weir
  63. [SI-LIST] Re: How to Measure Ground Noise, ji-wei_du
  64. [SI-LIST] Capacitivly Coupled Interfaces, Moeller, Merrick
  65. [SI-LIST] Re: Decoupling capacitors, Joe Paul M
  66. [SI-LIST] Re: Capacitivly Coupled Interfaces, steve weir
  67. [SI-LIST] 2006 EMC Symposium in Singapore, EMC Singapore
  68. [SI-LIST] Re: si-list Digest V5 #210, Daniel Chow
  69. [SI-LIST] IBIS Summit Second Call for Papers - DAC June14th, 2005, Anaheim CA, Syed Huq
  70. [SI-LIST] Estimate ISI with S parameters -- Using TDR to do SDD21 correlation?, John Lin (林朝煌)
  71. [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation?, John Lin (ææç)
  72. [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation?, steve weir
  73. [SI-LIST] Modal Currents and Voltages, Jones Edward
  74. [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation?, Chris Cheng
  75. [SI-LIST] Re: Estimate ISI with S parameters -- Using TDR to do SDD21 correlation?, Chris Cheng
  76. [SI-LIST] How to simulate 2 components each having its own process file in Hspice, Jing Wu
  77. [SI-LIST] How to simulate 2 components each having its own process file in Hspice, Jing Wu
  78. [SI-LIST] SI career path, John wilson
  79. [SI-LIST] Re: How to simulate 2 components each having its own process file in Hspice, Mohammad Ali
  80. [SI-LIST] Hi-pot test requirement for router., ªü¥È
  81. [SI-LIST] 10-Layer Stack up, sunil bharadwaz
  82. [SI-LIST] some question about JFET or MOSFET, dave
  83. [SI-LIST] Re: some question about JFET or MOSFET, Christopher.Jakubiec
  84. [SI-LIST] Re: 10-Layer Stack up, Thomas McGonigle
  85. [SI-LIST] Embedded Resistors, David Greig
  86. [SI-LIST] Definition of spreading inductance, Grasso, Charles
  87. [SI-LIST] Re: Embedded Resistors, Chris Cheng
  88. [SI-LIST] Wide input range LDO, Adeel Malik
  89. [SI-LIST] Re: Wide input range LDO, Adeel Malik
  90. [SI-LIST] power spectral density, timoceous
  91. [SI-LIST] starter, peter strauss
  92. [SI-LIST] R: starter, Guasti Giovanni
  93. [SI-LIST] Re: starter, peter strauss
  94. [SI-LIST] Determination of relative permittivity, Matthias Bergmann
  95. [SI-LIST] SI models at MGH speeds, sunil.mekad
  96. [SI-LIST] Calculating the Z0 of a trace, farid syed
  97. [SI-LIST] Re: Calculating the Z0 of a trace, Cosentino, Tony
  98. [SI-LIST] unsubscribe, Vivek-Fpga SHARMA
  99. [SI-LIST] Re: Determination of relative permittivity, Xin Wu
  100. [SI-LIST] Re: SI models at MGH speeds, Muranyi, Arpad
  101. [SI-LIST] Re: S11 or S21, Ming Tsai
  102. [SI-LIST] Re: FW: SI models at MGH speeds, Syed Huq
  103. [SI-LIST] DDR2 on-die termination 75ohm and 50ohm, ¤p¶h
  104. [SI-LIST] Scale option in Hspice, Jing Wu
  105. [SI-LIST] High speed signal on top layer, George Dai
  106. [SI-LIST] RF design guidelines??, SanjayKumar Vasamreddy
  107. [SI-LIST] ETX -module EBD model, De Paepe, Kristiaan
  108. [SI-LIST] Re: ETX -module EBD model, Dr. Edward P. Sayre
  109. [SI-LIST] Re: High speed signal on top layer, George Dai
  110. [SI-LIST] Simulation of Frequebcy Selective (FSS) and Periodic (PS) Structures in HFSS, mehdi hosseine
  111. [SI-LIST] ISI Jitter, Jayaprakash
  112. [SI-LIST] Re: Scale option in Hspice, Jing Wu
  113. [SI-LIST] Decoupling Using 3-Terminal Capacitor, Himanshu Arora
  114. [SI-LIST] Re: Decoupling Using 3-Terminal Capacitor, Himanshu Arora
  115. [SI-LIST] N-port s-parameter, TerenceHsieh




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