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[SI-LIST] Re: PI Analysis about Core Power Supply

From: Zhangkun <zhang_kun@xxxxxxxxxx>
To: Wei Zhou <wzhou@xxxxxxxxxxx>
Date: Mon, 09 May 2005 10:43:44 +0800
RE: [SI-LIST] Re: PI Analysis about Core Power SupplyWei
Sorry, I do not mean that there is problem in the IC from Marvell. All these IC 
are of high end IC, which is similar to the product of Marvell. Therefore, I 
mentioned Marvell.

Best Regards

Zhangkun
2005.5.9
  ----- Original Message ----- 
  From: Wei Zhou 
  To: zhang_kun@xxxxxxxxxx 
  Sent: Monday, May 09, 2005 8:52 AM
  Subject: RE: [SI-LIST] Re: PI Analysis about Core Power Supply




  Hi, Zhang Kun,

  Which Marvell device are you currently using?

  Wei

  -----Original Message-----
  From: si-list-bounce@xxxxxxxxxxxxx on behalf of zhangkun 29902
  Sent: Sun 5/8/2005 5:26 PM
  To: istvan.novak@xxxxxxx
  Cc: si-list
  Subject: [SI-LIST] Re: PI Analysis about Core Power Supply

  Dear all

  I have read the good advices. Thank you for your advice. Based on the advice, 
I think it is the most important is to request power data from the chip vendor.

  Is there any SI/PI engineer from chip vendor, such as Marvell?

  Best Regards

  Zhangkun
  2005.5.9

  ----- Original Message -----
  From: Istvan Novak <istvan.novak@xxxxxxx>
  Date: Sunday, May 8, 2005 10:27 pm
  Subject: [SI-LIST] Re: PI Analysis about Core Power Supply

  > Dear Zhangkun,
  >
  > As others suggested, your first line of attack is to request this
  > data
  > fromn
  > the chip vendor.
  >
  > If you cannot get this data from the chip vendor, you are left
  > with
  > speculations.
  > If you have the maximum current draw of the core, you can
  > speculate about
  > the biggest transients it can create.  It could be relatively
  > quiet,
  > creating only a
  > small change in current, or it can vary widely, almost zero to
  > 100%.
  >
  >
  > If you want to save time and get a safe design the first time, you
  > may
  > need to
  > assume that the current can switch between zero and 100%.  There
  > is always
  > some leakage, so the current will never go down to zero, plus the
  > maximum is
  > dependent on process, temperature and voltage, unless you can sort
  > out
  > those
  > details before you have to design the PDN, the safe bet is just to
  > use
  > the extremes.
  > This approach is more warranted as your frequency of interest goes
  > down.Even if fast transients in the core current are limited by
  > proper core
  > design,
  > 'slow' transients, say in the microseconds or even millisecond
  > range, will
  > most likely be a full 'minimum' to 'maximum' current swing.
  >
  >
  > Regards,
  > Istvan
  >
  >
  > Zhangkun wrote:
  >
  > >Dear All
  > >In current work, I am studying core power supply. The voltage of
  > core power is very low (0.9V-1.2V) and the power consuming is very
  > high (dozens of Amperes). There is often power integrity problem
  > in the frequency domain from 10MHz to 20MHz. The solution is very
  > easy that discrete caps should be added on the PCB.
  > >
  > >My problem is that the PI problem is found out until the first
  > edition has been produced. Then the decoupling caps is determined.
  > I want to determine the decoupling caps before the first edition
  > is produced in order to quicken the design flow. Therefore, I
  > should know the current noise source. I have been looking for the
  > paper about how to get the core power consuming in IEEE electrical
  > library. However, I have not found any useful paper.
  > >
  > >I hope I have express myself clear. Any advice is prefered.
  > >
  > >Best Regards
  > >
  > >Zhangkun
  > >2005.5.8
  > >
  > > 
  > >
  >
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[SI-LIST] Re: PI Analysis about Core Power Supply

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