Typically, data sheets spec. max. overshoot at VDD+0.3V and min. =
undershoot as GND-0.3V. Meeting these specs. usually requires adding =
series R's to the offending traces.
I have seen several SDRAM data sheets and at least one CPLD data sheet =
that provide a much more detailed spec. A typical SDRAM spec., for =
instance, allows VDD+2V and GND-2V as long as the duration is not =
greater than 3ns.
1) Are the SDRAM designers doing something unique with the IC pad design =
that allows these larger shoots or are they simply doing a better job =
specifying the extents?
2) What are some of the things that can go wrong if the shoots are too =
large?
2a) Is turning on the protection diodes the only concern?
3) What is the root cause of large shoots?
3a) The inductance of the lead frame seems to be a large contributor.
Thanks,
David
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