FreeLists / si-list / [SI-LIST] Re: SDRAM bus termination

["Tom Biggs" <tbiggs@xxxxxxxxxxxxxxxxxxxxx>]

Point-to-point is a special case.

Check out Micron's site. They have an app note for doing point-to-point
to DDR RAM using only a single series termination on the data bus. And
on the address/control bus, if you run the trace to a routing via, then
route from the via in a 'star' with equal length legs to all the SDRAM,
then the address shouldn't need the parallel termination either. There
is enough capacitance so that there is no over/undershoot.

It all depends on your drivers, memory, and cycle time. So be careful
and run simulations if you are doing a new design.

   -tom

-----Original Message-----
From: Raj, Shankar [mailto:Shankar.Raj@xxxxxxx]=20
Sent: Thursday, May 01, 2003 9:57 PM
To: 'shane.san.miguel@xxxxxxxxx'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SDRAM bus termination



Hi Shane,

I am having point-to-point data interconnections between chipset and
stacked DDR's(SSTL2). The length varies from 3 - 5 inches and there is
no parallel termination to 1.25V. The signal quality and timings are
fine wrt simulation, but I would like to know whether there are any
implcations of not using a parallel termination to 1.25V. I read your
mail, but couldn't understand clearly. It will be of great help if u can
explain the same.

Thanks and Regards,
Shankar V
Force Computers
Bangalore

-----Original Message-----
From: San Miguel, Shane [mailto:shane.san.miguel@xxxxxxxxx]
Sent: Wednesday, 30 April 2003 1:34 AM
To: ganesancp@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SDRAM bus termination



The SDRAM stuff will work fine in point to point config as long as the =
=3D
data bus is short.  Shouldn't be a concern even though SSTL specs =3D
specify a high-z state.  I have no knowledge of the FPGA side of your =
=3D
situation but as long as it doesn't use the DQS preamble/postamble to =
=3D
set up any data window timings you'll be fine.  You can't do the =3D
preamble/postamble with point to point.  I've seen point to point SDRAM
=3D and DDR DRAM on testers using FPGAs and point to point with no =
issues.
=3D Without termination there WILL BE a charge up time for the data bus, =
1
=3D or two bits worth maybe, depends.  You'll see this represented as =
the
=3D high/low swing gradually rising in DC level over a couple of
successive =3D reads (or bits).  As long as you know this is happening =
it
shouldn't be =3D an issue.

Shane San Miguel=3D20
Product Engineer=3D20
Platform Memory Operations=3D20
Intel Corporation=3D20


=3D20

=3D20



-----Original Message-----
From: ganesancp [mailto:ganesancp@xxxxxxxxxxx]
Sent: Tuesday, April 29, 2003 9:33 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] SDRAM bus termination



Hello SI experts,

I am designing a board with one SDR SDRAM and i want to connect =
this=3D20
SDRAM to a Xilinx Virtex-E FPGA in another board. SDRAM interface=3D20
will be working at 120MHz and there is no other component in the =
bus=3D20
(point-to-point).=3D20

Any termination suggested for the data bus and any other SI related=3D20
issues expected in this configuration?

Regards,
Ganesan

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