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Thread Index for si-list, 05-2002

[si-list] || [05-2002 Date Index] [05-2002 Thread Index]

  1. [SI-LIST] Re: Trace Bends, Doug McKean
  2. [SI-LIST] Design rule on immunity not effective, Douglas C. Smith
  3. [SI-LIST] Diff 2 Load, pikeda
  4. [SI-LIST] Re: Serpentine/Spiral Lines (was Re: Trace Bends), Tsuk, Michael
  5. [SI-LIST] Re: Diff 2 Load, Ivanov, Evghenii
  6. [SI-LIST] signal integrity in circuit pack development process, Dennis Schmitz
  7. [SI-LIST] S-parameter simulation in NSpice, Yu Liu
  8. [SI-LIST] To the list administrator, David Instone
  9. [SI-LIST] SJ/ Boston-Sr SI FAE's Needed...Ref fees paid!, Gary-Paul Congdon
  10. [SI-LIST] Re: looking for (differential) crosstalk calculator on the web, prathap muthana
  11. [SI-LIST] Limits of Wide Band Match to Reactive Impedances, Christian Schuster
  12. [SI-LIST] looking for (differential) crosstalk calculator on the web, Doug Brooks
  13. [SI-LIST] DDR DRAM, Ravinder Ajmani
  14. [SI-LIST] Re: DDR DRAM, Bill Dempsey
  15. [SI-LIST] Re: Voltage droop analysis_ load current model, Larry Smith
  16. [SI-LIST] Re: Frequency criterion in power plane_Power integrity, Larry Smith
  17. [SI-LIST] Ccomp in HSPICE, Timothy Coyle
  18. [SI-LIST] [Crosstalk calculation], You Se Ho
  19. [SI-LIST] Decoupling capacitors, Alexander.Shapira
  20. [SI-LIST] Re: [Crosstalk calculation], Ched-Chang Chai
  21. [SI-LIST] Re: Decoupling capacitors, Michael_Greim
  22. [SI-LIST] 3D Field Solvers, Bill Dempsey
  23. [SI-LIST] Stub Definition, Doug Brooks
  24. [SI-LIST] Re: Stub Definition, Michael_Greim
  25. [SI-LIST] Package Resonance, Neeraj Pendse
  26. [SI-LIST] Re: Ccomp in HSPICE, Mirmak, Michael
  27. [SI-LIST] DDR SDRAM, Ched-Chang Chai
  28. [SI-LIST] Re: Package Resonance, Dan Swanson
  29. [SI-LIST] Re: DDR SDRAM, Kurt Blacker
  30. [SI-LIST] Anyone with DDR2 experience?, Patrick O'Shea
  31. [SI-LIST] Board via characteristics (fwd), David Hoover
  32. [SI-LIST] Re: Board via characteristics (fwd), Aubrey_Sparkman
  33. [SI-LIST] Re: Frequency criterion in power plane_Power integr ity, Chris Cheng
  34. [SI-LIST] Limiting number of nodes in HSPICE .probe output files, Ingraham, Andrew
  35. [SI-LIST] Re: Limiting number of nodes in HSPICE .probe output files, Bill . Cohen
  36. [SI-LIST] Re: Anyone with DDR2 experience?, msharpes
  37. [SI-LIST] Re: Frequency criterion in power plane_Power integr ity, Larry Smith
  38. [SI-LIST] Eye diagrams in XTK on PC, Timothy Coyle
  39. [SI-LIST] Edge Coupled Symmetrical Stripline Questions, Al Owens
  40. [SI-LIST] Re: Eye diagrams in XTK on PC, Ron . J . Morneault
  41. [SI-LIST] loosely vs tightly coupled differential pairs, David Kaiser
  42. [SI-LIST] Re: Edge Coupled Symmetrical Stripline Questions, Sanchez, Louis
  43. [SI-LIST] SI Engineer - Available, Sainath Nimmagadda
  44. [SI-LIST] .NET Statements in HSPICE for S-Parameters, Chien-Min Lin
  45. [SI-LIST] Re: .NET Statements in HSPICE for S-Parameters, Ross Jatou
  46. [SI-LIST] Re: loosely vs tightly coupled differential pairs, Bill Dempsey
  47. [SI-LIST] Re: Limiting number of nodes in HSPICE .probe outp, Jay Shenoy
  48. [SI-LIST] Solder & Paste Mask Properties, Adeel Malik
  49. [SI-LIST] Signal Integrity Seminar, May 21, 2002, Boxborough Massachusetts, Kathy Breda
  50. [SI-LIST] Effect of Driving current, Ched-Chang Chai
  51. [SI-LIST] Re: Effect of Driving current, Ingraham, Andrew
  52. [SI-LIST] DDR SDRAM 857 CLOCK DRIVER, evillaf
  53. [SI-LIST] Sr. SI opportunity, tal Sophia
  54. [SI-LIST] Two layer board impedance calculation, Goutham . S
  55. [SI-LIST] Differential noise, rajat . chauhan
  56. [SI-LIST] Re: Differential noise, Wayne Cooke
  57. [SI-LIST] Re: Solder & Paste Mask Properties, Bill Dempsey
  58. [SI-LIST] Re: Two layer board impedance calculation, Ravinder Ajmani
  59. [SI-LIST] Announcement, Scott McMorrow
  60. [SI-LIST] bit sequence generator for SPICE, Beal, Weston
  61. [SI-LIST] Propagation velocity vs. temperature in PCB traces, Eric Goodill
  62. [SI-LIST] Re: Propagation velocity vs. temperature in PCB traces, Nirmal Sharma
  63. [SI-LIST] Re: bit sequence generator for SPICE, CCT20ES
  64. [SI-LIST] IBIS Model for a Tri_State Pin, Craciun, Liviu-Dumitru
  65. [SI-LIST] Common Mode vs. Even Mode, Mirmak, Michael
  66. [SI-LIST] Cap discontinuity, mittalr@xxxxxxxxxx
  67. [SI-LIST] Re: Common Mode vs. Even Mode, Clewell, Craig
  68. [SI-LIST] Signal Integrity related papers on SiQual's website, Rob Hinz
  69. [SI-LIST] Re: IBIS Model for a Tri_State Pin, Ingraham, Andrew
  70. [SI-LIST] Re: Cap discontinuity, mittalr@xxxxxxxxxx
  71. [SI-LIST] Cross-talk, which one is bigger?, Zhenhua Fan
  72. [SI-LIST] Re: Cross-talk, which one is bigger?, Ched-Chang Chai
  73. [SI-LIST] a signal integrity problem, Juan Manuel
  74. [SI-LIST] Labelling waveforms in XTK, Siva kumar
  75. [SI-LIST] FW: Re: Cap discontinuity, Loyer, Jeff W
  76. [SI-LIST] Jitter from Crosstalk, Ray Anderson
  77. [SI-LIST] Re: Labelling waveforms in XTK, Chris Rokusek
  78. [SI-LIST] Unable to unsubscribe!!!!!!!!!!!!!!!, Doug
  79. [SI-LIST] Re: Jitter from Crosstalk, Volk, Andrew M
  80. [SI-LIST] Re: Unable to unsubscribe!!!!!!!!!!!!!!!, Ingraham, Andrew
  81. [SI-LIST] Re: s2ibis2 Problem, Feldman, Richard
  82. [SI-LIST] Wire impedance at HF, Tabatchnick, Justin
  83. [SI-LIST] FW: Wire impedance at HF, Tabatchnick, Justin
  84. [SI-LIST] FW: FW: Wire impedance at HF, Tabatchnick, Justin
  85. [SI-LIST] Resistivity of Tin/lead Plating, Adeel Malik
  86. [SI-LIST] problems encountered extracting radiation losses, Jan Vercammen
  87. [SI-LIST] Test, Charles Grasso
  88. [SI-LIST] PCIX AND Tprop, Brahim Koudssi
  89. [SI-LIST] Re: PCIX AND Tprop, mittalr@xxxxxxxxxx
  90. [SI-LIST] Re: problems encountered extracting radiation losses, Christian Schuster
  91. [SI-LIST] Re: Entry level RF book, Rob Hinz
  92. [SI-LIST] Re: Pole/Zero Extraction from measured S-parameter, Teo Yatman
  93. [SI-LIST] [Fwd: Entry level RF book], Jochen Feldhaar
  94. [SI-LIST] Info on Capacitive loading of devices, Sreejith Varma
  95. [SI-LIST] Re: Info on Capacitive loading of devices, Ingraham, Andrew
  96. [SI-LIST] Attaching coax cable to board, mittalr@xxxxxxxxxx
  97. [SI-LIST] FWD: Signal Integrity Position, Hassan O. Ali
  98. [SI-LIST] Re: FWD: Signal Integrity Position, Chris Cheng
  99. [SI-LIST] Waveform Correlation, Abe Riazi
  100. [SI-LIST] Sweep voltage source for EMI study, =?big5?b?u6+kaLPHXChTLiBDLiBDaGFvXCk=?=
  101. [SI-LIST] FPC Cable Modeling, Roger_Wu
  102. [SI-LIST] [SI-LIST]: Design a shielded differential line, PRIEUR, Olivier
  103. [SI-LIST] THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON EMC - NEW VENUE! NEW CALL FORPAPERS, Elya B. Joffe
  104. [SI-LIST] Re: [SI-LIST]: Design a shielded differential line, Dan Swanson
  105. [SI-LIST] PCI Timing Q?, Brahim Koudssi
  106. [SI-LIST] Re: PCI Timing Q?, Ingraham, Andrew
  107. [SI-LIST] Re: Decoupling capacitors - mesh density, Ray Anderson
  108. [SI-LIST] Using W-element in HSPICE, Bob Patel
  109. [SI-LIST] Re: Using W-element in HSPICE, Michael_Greim
  110. [SI-LIST] PCI CLOCK AND DATA IN HSPICE, Brahim Koudssi
  111. [SI-LIST] Errata Sheet for Wadell's "Transmission Line Design Handbook", Ray Anderson
  112. [SI-LIST] Re: Errata Sheet for Wadell's "Transmission Line Design Handbook", Christian Schuster
  113. [SI-LIST] list server outage, Ray Anderson
  114. [SI-LIST] Graduating student looking for position, zanella, fabrizio



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