FreeLists / si-list / [SI-LIST] Re: Frequency criterion in power plane_Power integrity

[Larry Smith <Larry.Smith@xxxxxxx>]

Zhiping - the frequencies mentioned in previous examples have nothing
to do with the operating frequency of the core or I/O circuits.  They
are the corner frequencies where the inductance impedance becomes higher
than the target impedance.

In your diagram below, the voltage source (VRM) is on the left and the
load is on the right.  The chip load wants to look out and see a
voltage source with the target impedance (or less) from high frequency
all the way down to DC.  If we drop 5% or more voltage across lpackage,
the circuits may malfunction, loose data, fail to meet timing, etc.
You are correct that the only voltage that really matters is
node2-Gnd2.  But it is going to be really hard to maintain the voltage
at node2-Gnd2 if excessive voltage is dropped across Lpackage.

The on-chip capacitance delivers the current from high frequency down
to some frequency where the on-chip capacitor impedance becomes higher
than the target impedance.  Below that frequency, current must come in
through the inductor.  A good way to look at this is a power filter
with lots of series inductors and parallel capacitors, all the way from
the VRM to the chip.  A better way to look at it is a transmission line
that has an impedance the same as the target impedance.  Close to the
chip, the lumped elements of the transmission line must be small enough
to support the frequency that the chip demands, possibly GHz.  As you
move away from the chip and closer to the VRM, the transmission line
does not have to support as high of frequency at each lumped element.
The L's and C's have longer time constants.  But the impedance of the
transmission line (sqrt(L/C)) must still meet the target impedance or
else voltage droop will occur along the way.

regards,
Larry Smith
Sun Microsystems

> Date: Wed, 08 May 2002 14:05:40 -0700
> From: Zhiping Yang <zhiping@xxxxxxxxx>
> X-Accept-Language: en
> MIME-Version: 1.0
> To: Larry.Smith@xxxxxxx
> CC: si-list@xxxxxxxxxxxxx, sghsu55@xxxxxxxxxxxx
> Subject: Re: [SI-LIST] Re: Frequency criterion in power plane_Power integrity
> Content-Transfer-Encoding: 7bit
> 
> Larry,
> 
> I can not fully agreed with you on the conclusions from your example.
> Here is the plot:
> 
>          ______node 1_____Lpackage___ node2
>          |
>      Zpcb
>          | _____Gnd1__________________GND2
> 
> As a designer, you may only care about the voltage noise at the die side
> node2 (Node2-Gnd2).  In your example, the 5% voltage drop you
> mentioned is across the  Lpackage (Node1-node2), which may not
> be important. If you correctly select the Zpcb( for example, let it be
> capacitive), you may be able to get higher operating frequency than
> the frequency you mentioned in the examples for the same package.
> 
> Thanks.
> 
> Zhiping
> 
> Larry Smith wrote:
> 
> > Sogo - the current transition time has a lot to do with inductance and
> > current magnitude.  The governing equation is V = L*di/dt.  Usually, we
> > do not want to see more than 5% voltage drop on our power rail and that
> > sets V in the above equation.  L is a property of the packaging.  The
> > core power path for a microprocessor might have 50pH loop inductance.
> > The current transient might be 50 amps from a 1 V supply.  Now that we
> > have defined L, di and V, we can calculate the transition time, dt =
> > L*di/V = 50pH*50A/.05V=50nSec.
> >
> > In other words, if we try to draw 50 amps out of a 50pH inductance in
> > less than 50 nSec, the voltage is going to droop more than 5% of 1V.
> > The GHz frequency associated with a 50nSec rise time is
> > 0.35/50nSec=7MHz.  This example has been for a microprocessor whose
> > core demands lots of current at a low voltage.  The fast 50 amp current
> > transient simply is not going to make it out of the 50pH package
> > inductance.
> >
> > Let's take another example of a 3.3V memory Dimm that draws 1 amp of
> > transient current.  Perhaps the equivalent loop inductance for the Dimm
> > power supply is 1 nH.  By the same calculation, dt =
> > 1nH*1A/(3.3*.05)=6nSec.  The frequency associated with 6nSec is
> > .35/6nSec=57MHz.  In other words, the Dimm can draw power from the
> > mother board from DC up to 57 MHz.  Above that frequency, the power
> > will have to come from onboard the Dimm.
> >
> > Please note that these calculations assume that all current is in the
> > Vdd/Gnd loop.  If signal return current gets involved, the problem is
> > much more complicated.  A simple target impedance between Vdd and Gnd
> > is a good starting point, but SSN analysis involving Vdd, Gnd and
> > signals should be done after that.
> >
> > regards,
> > Larry Smith
> > Sun Micorsystems
> >
> > > From: "sogo" <sghsu55@xxxxxxxxxxxx>
> > > To: "'Larry Smith'" <ldsmith@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
> > > Subject: RE: [SI-LIST] Frequency criterion in power plane_Power integrity
> > > Date: Wed, 8 May 2002 05:36:44 +0800
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> > >
> > > Hi Larry,
> > >   I'm pleasure to get your message and appreciate with lots of paper you
> > > wrote in this topic. Thank for your detail answer. I'm wonder the
> > > frequency band in PC board is so low, only 35MHz. In my project, I would
> > > like to simulate the power impedance of PDN in MB. However, the PDN of
> > > MB is linked to DDR through DIMM connector. I'm curious that why you
> > > define the rise time of PC board only 10ns. If the transient current is
> > > from northbridge, I believe the transient time is a couple of ns
> > > recently. That is said, the frequency band is about 350MHz. Is it right?
> > > In this frequency range, single node modeling of power plane is not
> > > sufficient. I have done some simulations, the results indicated the
> > > accurate model of power plane is necessary in modern high speed digital
> > > system design.
> > > Thank for your assistances in advance.
> > > Best regards
> > >
> > > -----Original Message-----
> > > From: Larry Smith [mailto:ldsmith@xxxxxxxxxxxxxxxxxx]
> > > Sent: Wednesday, May 08, 2002 12:10 AM
> > > To: si-list@xxxxxxxxxxxxx; sghsu55@xxxxxxxxxxxx
> > > Subject: Re: [SI-LIST] Frequency criterion in power plane_Power
> > > integrity
> > >
> > > Sogo - This is a very important question.  By using the target
> > > impedance concept in the frequency domain, we can guarantee that a
> > > certain voltage tolerance is met in the time domain.  But, at how high
> > > of frequency must we meet the target impedance?  Obviously, we don't
> > > have to meet the target impedance at 1 teraHertz.
> > >
> > > The answer depends upon the rise and fall times of the current
> > > transient.  The rise time is different at various positions of the
> > > circuit.  The current transition times at several circuit positions
> > > might be as follows:
> > >
> > > circuit position        tRise      freq
> > > -----------------       -------    ----
> > > power connector          1 uSec    350 kHz
> > > pc board                10 nSec    35  MHz
> > > silicon gates           .1 nSec    3.5 GHz
> > >
> > > The frequency is found by the formula 0.35(GHz)/tRise(nSec).  Most of
> > > the energy associated with the rising or falling edges is below this
> > > frequency. If your power distribution system meets target impedance at
> > > the calculated frequency and all the way down to DC at the various
> > > points of the circuit, you are guaranteed to have a supply that stays
> > > within the voltage tolerance used in the target impedance calculation.
> > >
> > > regards,
> > > Larry Smith
> > > Sun Microsystems
> > >
> > > > Delivered-To: si-list@xxxxxxxxxxxxx
> > > > X-eGroups-Return: sghsu55@xxxxxxxxxxxx
> > > > Date: Mon, 06 May 2002 04:12:53 -0000
> > > > From: "sogo_hsu" <sghsu55@xxxxxxxxxxxx>
> > > > To: si-list@xxxxxxxxxxxxx
> > > > Subject: [SI-LIST] Frequency criterion in power plane_Power integrity
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> > > >
> > > > Hi all,
> > > >   In high-speed digital system, power integrity becomes an important
> > > > issue right now. Some one evaluated power integrity in the quanity of
> > > > frequency dependent impedance of power plane, such as target
> > > > impedance. As we know, the impedance shall be maintained over a wide
> > > > band. But, what's the criterion? Knee frequency ? bandwidth of clock
> > > > pulse? or harmonics of clock?
> > > >   Thanks in advance.
> > > > Best regards,
> > > > Sogo
> > > >
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