FreeLists / si-list / [SI-LIST] Re: DDR SDRAM

[Kurt Blacker <Kurt@xxxxxxxxxxxxxxx>]

Chai,

I don't believe that the parallel termination resistors must be "tied" to
Vdd/2.
It is more that the voltage divider you create with the parallel termination
resistors must be such that the DC voltage on the transmission line rests at
Vdd/2.

For example if you are terminating a 50 ohm line you must use 100 ohms to
Vdd and 100 ohms to 0V.
This can burn up a lot of power from your DC supply. 
The reason for Vdd/2 is that this value will keep the DC bias on the
transmission line an equal distance from 
High and Low logic levels.

An alternative method to save power, is to create a voltage plane at Vdd/2
and attach a single 50 ohm resistor from the line to the plane.
I have not used this method for SSTTL2 specifically but have used it on
differential CML at 2.5GHz.

Kurt Blacker
Principal Hardware Engineer
Coriolis Networks Inc.
330 Codman Hill Road
Boxborough, MA 01719

Tel. 978-264-1904 x645
FAX.978-264-1929
Email: kurt@xxxxxxxxxxxxxxx


-----Original Message-----
From: Ched-Chang Chai [mailto:ched_chang@xxxxxxxxxxx]
Sent: Thursday, May 09, 2002 6:55 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR SDRAM



Dear SI experts,
For DDR SDRAM using SSTL_2 signaling, is there any particular reason why the

parallel termination resistors must be tied to Vtt=Vdd/2?
Thank you.
--
Regards,
Chai



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