FreeLists / si-list / [SI-LIST] Re: Voltage droop analysis_ load current model

[Chris Cheng <chris.cheng@xxxxxxxxxxxx>]

In most of commerical spice, there is M or multipling factor.
Pick your favorite vendors transistor model, make an invertor
chain with a strong first stage to mimic the clock buffer.
Mulitply it a few million times (or whatever # of gates your
silicon has) and put it inside a simple package model.
Chances is, your bulk cap is more than enough to handle a
properly design package.

BTW, how do you model the close loop gain of the voltage
regulator ? What is the equivalent circuit for a close 
loop voltage regulator ?

Chris

-----Original Message-----
From: sogo_hsu [mailto:sghsu55@xxxxxxxxxxxx]
Sent: Sunday, May 05, 2002 9:06 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Voltage droop analysis_ load current model



Hi all,
  I would like to simulate voltage regulator module connect to a 
power plane pair by equivalent circuit model. The equivalent model of 
VRM and bulk capaciators were built up. But, how to model the current 
load? Opt pulse function and estimate the maximun/minimun surge 
currents or something else?
  Thanxs in advance!

Sogo 

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