FreeLists / si-list / [SI-LIST] Re: Frequency criterion in power plane_Power integrity

[Larry Smith <ldsmith@xxxxxxxxxxxxxxxxxx>]

Sogo - This is a very important question.  By using the target
impedance concept in the frequency domain, we can guarantee that a
certain voltage tolerance is met in the time domain.  But, at how high
of frequency must we meet the target impedance?  Obviously, we don't
have to meet the target impedance at 1 teraHertz.

The answer depends upon the rise and fall times of the current
transient.  The rise time is different at various positions of the
circuit.  The current transition times at several circuit positions
might be as follows:

circuit position        tRise      freq
-----------------       -------    ----
power connector          1 uSec    350 kHz
pc board                10 nSec    35  MHz
silicon gates           .1 nSec    3.5 GHz

The frequency is found by the formula 0.35(GHz)/tRise(nSec).  Most of
the energy associated with the rising or falling edges is below this
frequency. If your power distribution system meets target impedance at
the calculated frequency and all the way down to DC at the various
points of the circuit, you are guaranteed to have a supply that stays
within the voltage tolerance used in the target impedance calculation.

regards,
Larry Smith
Sun Microsystems

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> Hi all,
>   In high-speed digital system, power integrity becomes an important 
> issue right now. Some one evaluated power integrity in the quanity of 
> frequency dependent impedance of power plane, such as target 
> impedance. As we know, the impedance shall be maintained over a wide 
> band. But, what's the criterion? Knee frequency ? bandwidth of clock 
> pulse? or harmonics of clock?
>   Thanks in advance.
> Best regards,
> Sogo 
> 
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