FreeLists / si-list / [SI-LIST] Re: On-die caps for IO supply

[olaney@xxxxxxxx]

This article addresses the general topic of on-chip power integrity: 
http://www.edadesignline.com/showArticle.jhtml?articleID=207100271

Regards,
Orin Laney

On Wed, 9 Apr 2008 10:32:35 -0400 "Stephane Tremblay"
<strembl1@xxxxxxxxxx> writes:
> Hi SI-Listers,
>        I am looking for a rule of thumb on the required on-die 
> capacitors needed for proper operation of a given IO (a DDR mem IO 
> in my case). I am looking for a number of "x" capacitance per IO.
> 
> My IO can be programmed to 18 Ohms of drive and the measured 
> slew-rate is slightly higher than 6 V/ns for both rise and fall. The 
> parasitic capacitance of this IO is about 3.5 pF. The toggle rate 
> could be as high as 2 Gbps so I expect the IO rail to recover within 
> reasonable limits within half a period.
> 
> I could always start by assuming the current I need just for the 
> transmission line (being a 50 Ohms one):
> 
> dI/dt = 6 V/ns / 50 Ohms = 120 mA / ns   (per IO)
> 
> but this basic current demand calculation neglected the parasitic 
> capacitance of 3.5 pF.
> 
> Some will say it is also greatly dependant of my power-gnd loop 
> inductance from IO to on-package decaps. On the other end, if my 
> noise spectrum is in the hundreds of MHz, I can't do much at the 
> package level to clean my die supply.
> 
>  So from your experience and knowledge, what would be a good start 
> as a required on-die capacitance required. I want to avoid my on-die 
> IO rail collapsing at a frequency that my package could not keep up.
> 
> Thanks for the answers,
> Steph.
>  
> 
> 
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