FreeLists / si-list / [SI-LIST] 答复: A Hspice question about current on W-element

[xuzhengrong <Zhengrong.Xu@xxxxxxxxxx>]

Hassan, 
Thanks for your reply. 

I also paid attention to the problem.

As we expect, i3(W1)=i4(W1)=i1(W1) =-i2(W1) when the nodes of OUT and
OUT_GND is open.

But when the nodes of OUT and OUT_GND connect to an input buffer as a load,
still i3(W1)=i4(W1)  i1(W1) =-i2(W1), and i3(W1) just has some transmission
delay to i1(W1) but has the same direction to i1(W1).

If  IN_GND and OUT_GND both of that connect to 0  are thought as the same
node,  why i4(W1) is not equal to i2(W1) or i3(W1) is not equal to i2(W1)
when i3(W1) has some transmission delay to i1(W1)?

How can I understand the current of the fourth node, i4(W1)?

 

Best Regards,

Zhengrong

  _____  

·¢¼þÈË: Hassan O. Ali [mailto:hassan@xxxxxxxx] 
·¢ËÍʱ¼ä: 2008Äê4ÔÂ8ÈÕ 20:25
ÊÕ¼þÈË: xuzhengrong
Ö÷Ìâ: Re: [SI-LIST] A Hspice question about current on W-element

 


You said in_gnd and out_gnd both connect to 0 so it is the same node hence
expect same current that is directed in the opposite direction to the source
current i1(W1) and same direction to i3(W1).

Hassan.


On Tue 08/04/08 5:55 AM , xuzhengrong Zhengrong.Xu@xxxxxxxxxx sent:

Hi all, 
I recently used Hspice to observe the current on a W-element. 

W-element is a four-ports element as a distributed transmission line. 

For example, 

W1 in gnd_in out gnd_out rlgcfile=w1.rlgc L=1, assuming that gnd_in 
and gnd_out both connect to 0. 

I used .print i1(W1) i2(W1) i3(W1) i4(W1) to observe corresponding i(in) 
i(gnd_in) i(out) i(gnd_out). 

I(gnd_in) is the return current of i(in), so i(gnd_in) should be the inverse

phase of i(in). The same to i(out) and i(gnd_out). 

The simulation results show that i1(W1)= - i2(W1) (as we have expected), but

i3(W1)= i4(W1) surprisingly. 

Why is i4(W1) equal to i3(W1) instead of i4(W1)=-i3(W1) in this simulation? 

Is anything wrong about my idea? 

Appreciate anything about it. 



Best Regards, 

Zhengrong 







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