FreeLists / si-list / [SI-LIST] serdes device locking issues

["Hari Shanker Gupta" <hari@xxxxxxxxxxxxxxx>]

Hi All

I am designing a ASIC, which uses Serdes as I/O module . I am stuck up with 
these design issues.

1. At start up of serdes device( using 8B/10B as encoding technique), when 
PLL of receiver-side is getting locked with incoming signal frequency and 
phase, what pattern  a transmitter should send at that initialization.

2.Can we transmit  1010101010101..(contiguous alternating pattern) as an 
initial pattern?

3. How much time a PLL in serdes system using 8B/10B technique takes to get 
locked?

4. Which type of PLL should be used at receiver and transmitter end? Analog 
or digital. And why?

5. As mentioned in a article, Hogge detector is used at receiver end. Whether 
it provide any additional benefit?

6. Is there any pulse shaping is used in serialized transmitted data, so that 
it provide best eye opening at receiver(lowest jitter).

waiting for reply.....
 
Please guide me to come out from these problem.


Thanking You



-- 
Regards

|------------------------------------|
|Hari Shanker Gupta                  | 
|SCI/ENGR                            |
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