FreeLists / si-list / [SI-LIST] Re: ADC Gnd Noise

[KEGAN@xxxxxxxxxxxxx]

If you are really seeing 2V overshoot/undershoot, then you're directly 
injecting noise straight into the power planes via the ESD diodes on 
the ADC.

KWE





hi,
   Thanks for the suggestion. We have measured analog ground noise 
with respect to digital ground and it is around 300mV(p-p) on the 
scope. Even if we subtract 60mV noise due to probe, the noise will be 
around 180mV(p-p). When there is no signal to ADC, the 8 LSB bits from 
ADC are toggleing. That is, ADC is seeing around 80mV(p-p) noise at 
its input. 
   
  The clock of 7.414MHz is generated using PLL inside the FPGA and is 
passed through a 3.3V to 5V transceiver having driving capacity of 
25mA. The clock output from the transceiver is routed to ADC without 
any sheilding. We are observing overshoots and undershoots of about 2V
(p-p) on the ADC clock, but there is no shift in the edges of the 
clock. 
  Yes, we have checked  both grounds and we are observing the noise of 
around 300mV(p-p). That is, AGND w.r.t AGND has 300mV(p-p), DGND w.r.t 
DGND has 300mV(p-p) and AGND w.r.t  DGND has 300mV(p-p).
   
  Thank you and regards,
  Deepak.
  

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