FreeLists / si-list / [SI-LIST] Re: NPU / DDR interface bug issue

["Christopher R. Johnson" <crjohnson11@xxxxxxxxxxx>]

 Jean-Pierre What is the full-bandwidth test doing?  Is the pattern that you
see in the defined memory space related to the pattern that was written
during the full bandwidth test, or just garbage?  The question is whether
theaddress to the memory is getting messed up during the full bandwidth
test.  Can you set or record the entire contents of memory before the test
tosee if there are any unexpected changes after the test fails?
Chris

BOUTHEMY JEAN PIERRE wrote: Hi Chris, The complete test procedure is the
following: 1- I write some defined words in a defined memory space 2- I read
this same memory space to make sure I find the value I wrote: it is always
the case 3- I run the full bandwith test 4- When the test fails, I read the
same memory space and I observe anythjing, but not the value I had written
inthe memory I will try the "freeze spray" on the DDR. Thank you,
Jean-Pierre-----Message d'origine----- De : si-list-bounce@xxxxxxxxxxxxx[1]
[mailto:si-list-bounce@xxxxxxxxxxxxx[2]] De la part de Chris Johnson
Envoy&eacu: mardi 10 avril 2007 16:36 À: BOUTHEMY JEAN PIERRE;
si-list@xxxxxxxxxxxxx[3] Objet : [SI-LIST] Re: NPU / DDR interface bug issue
When you say that the DDR is blocked, what do you mean? The interface is no
longer working at all? It is not unusual for a marginal problem to go away
when you load the lines in question by probing them. It could be that there
is a meta-stable condition that is affected by the slight change (usually
slowing down) of the bus signals caused by probing. You can see if probing
one particular line causes the problem to go away by removing probes until
itstops working again. Even with 3" wires, I'm not sure that your interface
signals should look all that bad, so it could be a signal integrity problem
as well. You can try using a resistive probe so that the ground issues are
not as much of a concern. See http://www.sigcon.com/Pubs/news/5_4.htm[4] .
You could also try spraying any suspect chips with "freeze spray" to see if
the change in temperature also affects the problem. If a cold chip runs
better, that also implies that it is a timing issue. Good Luck. Chris
JohnsonBOUTHEMY JEAN PIERRE wrote: =20 Hello SI experts, I have to solve for
a DDR interface issue when traffic is full bandwith (1Gb/s): DDR is then
blocked and we can not access to it anymore.=20 Note that this "should not
be" a card bug because it happens only on a few cards, about 2 or 3 protos
among more than 100 cards.=20 FYI, the Controller is an Intel Network
Processor IXP2400 and the DDR interface is running at 150MHz.=20 On one of
the fail cards, I have soldered some wires (about 3" long) on a few signals
(CS, WE, RAS, CAS, CK, DQS0 and DQ0) and attached 4 probes on CK, WE, DQS0
and DQ0. I have launched the full bandwith test on this card and observed
that it is now running OK for more than 118 hours without failing!!=20 The
scope signals are very poor on the scope (scope + probe bandwith >6GHz)
because of the too long wires and the ground connection which is very
poor.=20 But I can not understand why the interface is running OK for more
than 5 days, whereas it normally fails before 2 minutes of full bandwith
test!! Has someone already experienced such a case?=20 Could you please
explain if some stubs on signals could make the signal integrity better, or
ameliorates a timing, or so ...=20 Please remember that only 2 or 3 cards
among more than 100 have this issue, which means that it "should not" be a
design issue.=20 Thank you for your help, Regards,=20 Jean-Pierre.=20
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