FreeLists / si-list / [SI-LIST] Re: overshoot and undershoot different swing

["Jim (James) Antonellis" <janton@xxxxxxxxxxxx>]

Rajeev,

I see a few situations to consider:

1) ESD
2) Timing
3) Fidelity

The ESD structures typically dictate what is allowed for
over and under shoot and they are not necessarily identical=20
even after polarity has been taken into account. Some of the=20
(better?) specifications will provide an area_under_the_curve=20
specification for the over/under shoots.

In regards to timing and fidelity, these will be application
dependent. For example, one example bus may allow for a lot
of settling time before sampling and as such will tolerate
the time that the over/under shoot does not meet the logic=20
threshold. Kind of the same thing with fidelity except you=20
need to be careful of false transitions that may occur on=20
clocks/strobes if a sequence of underdampened over/under-
shoots occur (may be referred to as underdamped ringing in=20
some circles).=20

Jim


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Jim Antonellis=20

janton@xxxxxxxxxxxx

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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of rajeev.kommera@xxxxxxxxx
Sent: Tuesday, April 03, 2007 1:36 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] overshoot and undershoot different swing


Hi all,

We are having 76 MHZ clock output from FPGA in our design.
I am seeing on oscilloscope that the overshoot and undershoot is not
same.

I want to know whether it is necessary that overshoot and undershoot
values needed to be same? If yes then what factors effects the values to
be different?


Regards,
Rajeev.
Failing to Plan is Planning to Fail



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