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Thread Index for si-list, 04-2006

[si-list] || [04-2006 Date Index] [04-2006 Thread Index]

  1. [SI-LIST] Re: How to simulate length mismatch of PCB traces, steve weir
  2. [SI-LIST] H.264 Video Compression Asic Design, new Yahoo group;, Mark Apton
  3. [SI-LIST] Re: Theory v. practice, following Re: DesignCon quote, Ing. Giancarlo Guida
  4. [SI-LIST] Future Directions in IC and Package Design Workshop, FDIP'06, Ray Anderson
  5. [SI-LIST] Testing, Aaen Peter-r40889
  6. [SI-LIST] Signal Integrity Lead Position Available in San Jose, CA (perm/fulltime), James Van
  7. [SI-LIST] Cumulative probability (BER) vs sigma value of normal distributio n, chen_jinhua
  8. [SI-LIST] Re: Cumulative probability (BER) vs sigma value of normal distribution, Asbenson, Lyndell L
  9. [SI-LIST] Getting Hspice to accept numbers with mantissa's larger than 8 characters, Taha Amiralli
  10. [SI-LIST] How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E, Zhangkun
  11. [SI-LIST] Re: How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E, Wei Zhou
  12. [SI-LIST] Re: Getting Hspice to accept numbers with mantissa's larger than 8 characters, Muranyi, Arpad
  13. [SI-LIST] EM Modeling Position at Freescale Semiconductor Inc., Aaen Peter-r40889
  14. [SI-LIST] FW: Re: Theory v. practice, following Re: DesignCon quote, Ray Anderson
  15. [SI-LIST] Re: Getting Hspice to accept numbers with mantissa' s larger than 8 characters, Zabinski, Patrick J.
  16. [SI-LIST] Ethernet magnetics question, Joel Brown
  17. [SI-LIST] Re: Ethernet magnetics question, Curt McNamara
  18. [SI-LIST] Cisco Systems - Signal Integrity opening in San Jose, CA, Todd Westerhoff (twesterh)
  19. [SI-LIST] EM Modeling Position at Freescale Semiconductor Inc. [Tempe AZ], Aaen Peter-r40889
  20. [SI-LIST] Re: Getting Hspice to accept numbers with mantissa' s larger than 8 characters, Zabinski, Patrick J.
  21. [SI-LIST] Tradeoffs of split power plane vs. multiple power layers...., Jon Anderson
  22. [SI-LIST] HELP, Jon Anderson
  23. [SI-LIST] commands, Jon Anderson
  24. [SI-LIST] Testing again, Aaen Peter-r40889
  25. [SI-LIST] Re: Power Integrity measurement equipment, Heinrich . Smith
  26. [SI-LIST] Routing Signals Between PWB Layers, Doug Smith
  27. [SI-LIST] Input Impedance Changing, Yang Rui
  28. [SI-LIST] Re: Input Impedance Changing, Yang Rui
  29. [SI-LIST] Query about VIA modeling, vani.chandrasekharan
  30. [SI-LIST] SSTL2 classI without RS and RT on short length, Bernard Esteban
  31. [SI-LIST] Re: SSTL2 classI without RS and RT on short length, Peterson, James F \(FL51\)
  32. [SI-LIST] DDR2 SDRAM speed bins, Rajasekar
  33. [SI-LIST] Ferrite bead question, Joel Brown
  34. [SI-LIST] Re: DDR2 design, Briese Thad
  35. [SI-LIST] Re: Ferrite bead question, Curt McNamara
  36. [SI-LIST] SPI 2006 - Call For Participation: Program now available, Andre Grabinski
  37. [SI-LIST] Check it out, pavani . jella
  38. [SI-LIST] Ferrite bead question - Downloadable presentation, Grasso, Charles
  39. [SI-LIST] Re: Ferrite bead question - Downloadable presentation, Ray Anderson
  40. [SI-LIST] IC Corners and Etch Corners, Brianna . Bethel
  41. [SI-LIST] Miller Coefficient Factor (MCF), Matthew Unangst
  42. [SI-LIST] Re: IC Corners and Etch Corners, Abe Riazi
  43. [SI-LIST] Rogers4003 Board Characterization, ryansatrom
  44. [SI-LIST] Re: [SPAM] Rogers4003 Board Characterization, esayre
  45. [SI-LIST] Re: Rogers4003 Board Characterization, Weinberg, Richard \(Richard\)
  46. [SI-LIST] TDR measurement, Giuseppe DABUNDO
  47. [SI-LIST] How do two Random (Gaussian) Jitter specs add?, tom_cip_11551
  48. [SI-LIST] Re: TDR measurement, Ray Anderson
  49. [SI-LIST] Re: How do two Random (Gaussian) Jitter specs add?, art_porter
  50. [SI-LIST] Re: Effects of overshoot/undershoot on long-term reliability, Jeff Krinsky
  51. [SI-LIST] Re: R: Rogers4003 Board Characterization, Loyer, Jeff
  52. [SI-LIST] Return path for stripline between two power planes, geor_dai
  53. [SI-LIST] 4-Port VNA calibration question, Virendra
  54. [SI-LIST] Free Engineering Calculators, Allen Nejah
  55. [SI-LIST] Re: Impedance control with split ground planes, Balaji S
  56. [SI-LIST] Re: 4-Port VNA calibration question, Grossman, Brett
  57. [SI-LIST] About the DDR2 Data Timing Budget Calculation, YangJeffrey
  58. [SI-LIST] Patrick C Herbert/Cleveland/RA/Rockwell is out of the office., Patrick C Herbert
  59. [SI-LIST] Re: About the DDR2 Data Timing Budget Calculation, Peterson, James F \(FL51\)
  60. [SI-LIST] Re: About the DDR2 Data Tim ing Budget Calculation, dayedit
  61. [SI-LIST] impedance calculation, Shoran
  62. [SI-LIST] Question regarding return current in a differential pair, Michael Kotson
  63. [SI-LIST] Re: Question regarding return current in a differential pair, Mirmak, Michael
  64. [SI-LIST] Re: Question regarding return current in a differential pair, Aleksandr Oysgelt
  65. [SI-LIST] Ceramic Vs Tantalum for bulk bypassing, Joel Brown
  66. [SI-LIST] Re: Question regarding return current in a differential pair, Ray Anderson
  67. [SI-LIST] differential pair routing topology, Ivor Bowden
  68. [SI-LIST] Re: Question regarding return current in a differentialpair, Lee Ritchey
  69. [SI-LIST] Two SI application engineer positions open in Altera, San Jose., Binshen Meng
  70. [SI-LIST] Copper Pours, Robert . Havlik
  71. [SI-LIST] Re: Ceramic Vs Tantalum for bulk bypassing, steve . barton
  72. [SI-LIST] Inductance puzzle, Haikun Zhu
  73. [SI-LIST] SUBSCRIBE,, cao
  74. [SI-LIST] Re: Sr. Researcher on High-speed Interconnect Position Opening in Huawei(updated), JIA Gongxian
  75. [SI-LIST] varactor diode in clock delays, roman barkat
  76. [SI-LIST] Re: Copper Pours, Geoff Stokes
  77. [SI-LIST] Re: differential pair routing topology, Andrew Ingraham
  78. [SI-LIST] separation of analog and digital ground on a package, Dan Smathers
  79. [SI-LIST] Differential pair Impedance - Q on test data, Grasso, Charles
  80. [SI-LIST] Re: Differential pair Impedance - Q on test data, dmitry.a.smolyansky
  81. [SI-LIST] Question regarding current loop, Doug Brooks
  82. [SI-LIST] Re: Session of interest to SI engineers at DesignCon 2006, Pratt, Gary
  83. [SI-LIST] Re: Question regarding current loop, Lee Ritchey
  84. [SI-LIST] LVDS spacewire shield grounding, Tony Carosa
  85. [SI-LIST] Analysis about hot-plug, Zhangkun
  86. [SI-LIST] Re: Analysis about hot-plug, Chris Cheng
  87. [SI-LIST] Board Design Lead Position Available at San Jose Company (perm/fulltime), James Van
  88. [SI-LIST] DDR2 DQS Question, Henson, Bradley S
  89. [SI-LIST] Engineering Effort vs. Time, Peter Arnold
  90. [SI-LIST] Re: Engineering Effort vs. Time, Lee Ritchey
  91. [SI-LIST] Job Opening at Altera, Daniel Chow
  92. [SI-LIST] Re: Job Opening at Altera, Hassan O. Ali
  93. [SI-LIST] FPGA SI Issues in Space Applications, Sammit Adhya
  94. [SI-LIST] PI for analog device, DenisChen
  95. [SI-LIST] Job openings at CST of America, Fabrizio . Zanella
  96. [SI-LIST] Re: FPGA SI Issues in Space Applications, Tom Biggs
  97. [SI-LIST] Non monotonicity in daisy chain topology, vani.chandrasekharan
  98. [SI-LIST] Re: Non monotonicity in daisy chain topology, mohan.sithinathan
  99. [SI-LIST] Analog/Digital vss connection for a PLL IC, Bi Han
  100. [SI-LIST] Re: Maximum Current, Dunbar, Tony
  101. [SI-LIST] Design For Manufacturing assessment Tools for PCB Designs, Salkow, Steven
  102. [SI-LIST] Re: Design For Manufacturing assessment Tools for PCB Designs, Ray Anderson
  103. [SI-LIST] E-mail address harvesting (WAS; Re: Signal integrity and simulation), Andrew W. Riley III
  104. [SI-LIST] Effects of solder layer on exposed traces, Sean McDevitt



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