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[SI-LIST] Re: SSTL2 classI without RS and RT on short length
- From: "Peterson, James F \(FL51\)" <james.f.peterson@xxxxxxxxxxxxx>
- To: <scott@xxxxxxxxxxxxx>, <Ravinder.Ajmani@xxxxxxxxxxxxxx>
- Date: Mon, 10 Apr 2006 07:51:46 -0500
Scott -=20
You've mentioned DC wander and reduced margin when there is no
termination (and I believe you). Do you know of PRBP that will show
this?...... and maybe a data rate/length example (e.g. 1/4 wavelength
resonance)? I'd like to see if I can catch it on my simulator.
thanks,
Jim Peterson
Honeywell=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Scott McMorrow
Sent: Friday, April 07, 2006 3:27 PM
To: Ravinder.Ajmani@xxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SSTL2 classI without RS and RT on short length
Ravinder
Ah yes, it is sometimes possible. The key to your success was the use
of series termination. This de-Qs the bus resonance, which can kill. =20
The original question wanted to know if a DDR bus could be designed
without either series or parallel termination.
The DC wander occurs when no termination (or poorly matched termination
is used). Signal transitions excite a quarter wave resonance on the
bus. Differing bit patterns see either constructive or destructive
interference with the standing waves. This manifests itself as large
shifts in the average signal level, which I called DC wander, but is in
reality AC wander. It is very important to simulate a bus like this
rigorously, using patterns that will excite all possible resonance
points. It is also important to vary the trace length and Er in your
simulations across worst case expected ranges, since it is very easy to
miss a resonance by just a hair, and find that your bits lay directly on
top of it during production.
scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed(r) is the registered service mark of Teraspeed Consulting
Group LLC
Ravinder.Ajmani@xxxxxxxxxxxxxx wrote:
>
> Scott,
>
> I have implemented point-to-point SSTL2 200 MHz design without Rt.=20
> My data bus is 32 bits wide, and I had to use Rs to match the DRAM=20
> impedance (the ASIC has a controlled impedance driver). I am using=20
> VDD supply to generate Vref. Of course I simulated it thoroughly for=20
> delay, reflection, and crosstalk. My next design will be for 240 MHz.
> I will appreciate if you could explain DC wander due to patterns run=20
> length.
>
> Thanks.
>
> Regards, Ravinder
> Server PCB Development
> Hitachi Global Storage Technologies
>
>
> Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
>
>
> *Scott McMorrow <scott@xxxxxxxxxxxxx>* Sent by:=20
> si-list-bounce@xxxxxxxxxxxxx
>
> 04/07/2006 06:29 AM
> Please respond to
> scott@xxxxxxxxxxxxx
>
>
> =09
> To
> esteban.bernard@xxxxxxxxxx
> cc
> si-list@xxxxxxxxxxxxx
> Subject
> [SI-LIST] Re: SSTL2 classI without RS and RT on short length
>
>
>
> =09
>
>
>
>
>
> Bernard
>
> At 250 MHz, you must have a resistor to Vtt in order to maintain DC=20
> balance around Vref. Otherwise your DC wander due to pattern run=20
> length will cause excessive timing and voltage margin loss
>
> Scott
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>
> http://www.teraspeed.com
>
> Teraspeed(r) is the registered service mark of Teraspeed Consulting=20
> Group LLC
>
>
>
> Bernard Esteban wrote:
> > Hi,
> >
> > I'm currently designing a board with fpga(U1) and a chip(U2) where=20
> > IO are in levels SSTL2. Both chip are BGA 1mm and 0.8mm.
> > 8 IO one-way U1 to U2, and 8 one-way U2 to U1.
> > So 16 lines point to point. Clock frequency is 250MHz in single data
> rate..
> > The two chips are very close, less than 1/2 inch.
> > I made schematics with Rs and Rt, but they takes a lot of place,
> even is
> > I use fpga integrated Rs.
> > I think this could be possible to connect these 2 chips without RS=20
> > and RT, but I dont have a simulator for my PCB router, and so, to=20
> > validate this solution.
> > I found some papers and discussions were RT is not used, other paper
> > were RS is not used.
> >
> > Did you try this idea or did you think this idea can works with good
> > reliability ??
> >
> > Regards,
> >
> > Bernard
> >
> > =20
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