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[SI-LIST] Re: SSTL2 classI without RS and RT on short length
- From: Ravinder.Ajmani@xxxxxxxxxxxxxx
- To: scott@xxxxxxxxxxxxx
- Date: Fri, 7 Apr 2006 12:15:41 -0700
Scott,
I have implemented point-to-point SSTL2 200 MHz design without Rt. My
data bus is 32 bits wide, and I had to use Rs to match the DRAM impedance
(the ASIC has a controlled impedance driver). I am using VDD supply to
generate Vref. Of course I simulated it thoroughly for delay, reflection,
and crosstalk. My next design will be for 240 MHz. I will appreciate if
you could explain DC wander due to patterns run length.
Thanks.
Regards, Ravinder
Server PCB Development
Hitachi Global Storage Technologies
Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
Scott McMorrow <scott@xxxxxxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
04/07/2006 06:29 AM
Please respond to
scott@xxxxxxxxxxxxx
To
esteban.bernard@xxxxxxxxxx
cc
si-list@xxxxxxxxxxxxx
Subject
[SI-LIST] Re: SSTL2 classI without RS and RT on short length
Bernard
At 250 MHz, you must have a resistor to Vtt in order to maintain DC
balance around Vref. Otherwise your DC wander due to pattern run length
will cause excessive timing and voltage margin loss
Scott
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Bernard Esteban wrote:
> Hi,
>
> I'm currently designing a board with fpga(U1) and a chip(U2) where IO
> are in levels SSTL2. Both chip are BGA 1mm and 0.8mm.
> 8 IO one-way U1 to U2, and 8 one-way U2 to U1.
> So 16 lines point to point. Clock frequency is 250MHz in single data
rate..
> The two chips are very close, less than 1/2 inch.
> I made schematics with Rs and Rt, but they takes a lot of place, even is
> I use fpga integrated Rs.
> I think this could be possible to connect these 2 chips without RS and
> RT, but I dont have a simulator for my PCB router, and so, to validate
> this solution.
> I found some papers and discussions were RT is not used, other paper
> were RS is not used.
>
> Did you try this idea or did you think this idea can works with good
> reliability ??
>
> Regards,
>
> Bernard
>
>
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