FreeLists / si-list / [SI-LIST] Re: How to embedded and to deembedded the clock to serial signal, such as GE and PCI-E

["Wei Zhou" <wzhou@xxxxxxxxxxx>]

Zhangkun,

A typical serial link like PCIE, GE have a PLL on the TX side and a clock data 
recovery circuit (CDR) on the RX side. The TX PLL multiply the reference clock 
up and latch data out. In a lot serial links, data is 8B/10B encoded to ensure 
enough transition edges for the CDR to recover the clock. In that sense, the 
clock is "embedded". 

The CDR on the RX side will try to figure out the right timing to sample data 
based on the data transition it was seeing. The CDR fundamentally is another 
PLL, the loop inside the CDR move the sampling edge back and forth to have it 
centered around the center of the data eye, thus recovering or "de-embeding" 
the clock and use the recovered clock to latch in data.

Wei
 
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx on behalf of Zhangkun
Sent: Tue 4/4/2006 8:51 PM
To: si-list
Subject: [SI-LIST] How to embedded and to deembedded the clock to serial 
signal, such as GE and PCI-E
 
Dear all
Recently, in our product, there is some problem in our product. The serial 
signal, such as GE and PCI-E, has error bits. We have found out the reason:
    1.The serial signal has crosstalk.
    2.The clock signal to PLL has crosstalk.
    3.The analog power of the PLL or the serial signal driver has large power 
noise.

I guess the basic reason is that the jitter of clock. Could anybody explain to 
me how the clock signal is embedded to and deembedded from the serial signal?

Best Regards

Zhangkun
2006.4.5


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