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Thread Index for si-list, 04-2005

[si-list] || [04-2005 Date Index] [04-2005 Thread Index]

  1. [SI-LIST] Re: [IBIS-Users] ODT topics, lgreen
  2. [SI-LIST] Grounding, HARIHARAN RAMLINGAM - RND
  3. [SI-LIST] Re: [Expert system], Ralf Bruening
  4. [SI-LIST] [Fwd: Re: Re: package SSN model accuracy requirements], Chuck Yuan
  5. [SI-LIST] PureMode VNA vs 4port VNA, Ray Anderson
  6. [SI-LIST] power distribution systems - general schemes, Kamran Azizi
  7. [SI-LIST] Senior level S/I consultant, Gary Schneider
  8. [SI-LIST] Regarding ibis for PCI-e connectors and more..., Roy M.
  9. [SI-LIST] Re: PureMode VNA vs 4port VNA], Brad Cole
  10. [SI-LIST] Re: PureMode VNA vs 4port VNA, Zabinski, Patrick J.
  11. [SI-LIST] Correction: PureMode VNA vs 4port VNA], Brad Cole
  12. [SI-LIST] Using Matlab for SERDES simulations, Zanella, Fabrizio
  13. [SI-LIST] Re: Using Matlab for SERDES simulations, Chris Cheng
  14. [SI-LIST] Lumped capacitance estimation, Sushil Kumar GUPTA
  15. [SI-LIST] Soldermask Impact Microstrip Impedance, Pang Ning
  16. [SI-LIST] How to Measure Ground Noise, ospyng
  17. [SI-LIST] Eye diagram measurement, Jayaprakash
  18. [SI-LIST] Re: How to Measure Ground Noise, Joe Paul
  19. [SI-LIST] Re: Eye diagram measurement - And leaves your teeth Shiny White Too!, Pratt, Gary
  20. [SI-LIST] Re: Soldermask Impact Microstrip Impedance, Aubrey_Sparkman
  21. [SI-LIST] Micro-connectors, Stephan Giesinger
  22. [SI-LIST] Inductive and Capacitive coupling, Doug Smith
  23. [SI-LIST] Re: Micro-connectors, Craig Clewell
  24. [SI-LIST] HSPCIE Simulation about Transmission Line, Zhangkun
  25. [SI-LIST] Re: HSPCIE Simulation about Transmission Line, sghsu55
  26. [SI-LIST] Re: creating an IBIS model..., race
  27. [SI-LIST] Batch simulation, race
  28. [SI-LIST] resend Re: How to Measure Ground Noise, Doug Smith
  29. [SI-LIST] Differential vs. SE, Propagation speed comparison, Chris McGrath
  30. [SI-LIST] Re: Differential vs. SE, Propagation speed comparison, zhangkun 29902
  31. [SI-LIST] IEEE-EMCS Santa Clara Valley Chapter Meeting on Tuesday April 12th, Ahmad Fallah
  32. [SI-LIST] Information required on 2D / 3D Field Solvers, Pankaj Kakkar
  33. [SI-LIST] Quality of package signal integrity tool, Pankaj Kakkar
  34. [SI-LIST] Question on Rogers4350 loss, jose_moreira
  35. [SI-LIST] Dispersion in Lossy Lines, Adrianna
  36. [SI-LIST] Re: Question on Rogers4350 loss, steve weir
  37. [SI-LIST] High Frequency Performance of Halogen Free BGA Substrates?, Neeraj Pendse
  38. [SI-LIST] Re: A short story, McCormick, Bob
  39. [SI-LIST] PC133 unbuffered design reference guide, jan . vercammen1
  40. [SI-LIST] Re: PC133 unbuffered design reference guide, steve weir
  41. [SI-LIST] New IBISCHK411 Executable available for download, Syed Huq
  42. [SI-LIST] SI & PD Experience position at Cisco Systems,Inc, Abdulrahman Rafiq
  43. [SI-LIST] FW: A short story, Tom Biggs
  44. [SI-LIST] split plane, Nitin Sood
  45. [SI-LIST] Re: split plane, Nitin Sood
  46. [SI-LIST] Common Mode Impedance., Moeller, Merrick
  47. [SI-LIST] Do you really ship products at BER 10e-xx ?, Chris Cheng
  48. [SI-LIST] Re: Do you really ship products at BER 10e-xx ?, Henson, Bradley S
  49. [SI-LIST] question about the pull-up resistors, david
  50. [SI-LIST] Test criterion of USB voltage drop test, Sogo Hsu
  51. [SI-LIST] SPI 2005 - early registration reminder, Andre Grabinski
  52. [SI-LIST] Re: SEU errors, Chirag Shroff (cshroff)
  53. [SI-LIST] Re: Test criterion of USB voltage drop test, Sogo Hsu
  54. [SI-LIST] SI Engineering Opportunity at Dell, Jim_Pankratz
  55. [SI-LIST] Eye diagram and port definition in IBIS, Muranyi, Arpad
  56. [SI-LIST] Any intenship positions related Signal Integrity?, manish khemani
  57. [SI-LIST] SSN and Crosstalk in Package, Zhangkun
  58. [SI-LIST] X-talk, Jayaprakash
  59. [SI-LIST] Thoughts on via sharing, Santangelo, Steven
  60. [SI-LIST] Re: Thoughts on via sharing, steve weir
  61. [SI-LIST] Re: SSN and Crosstalk in Package, Chris Cheng
  62. [SI-LIST] Need advice on basic 6-layer stackup, Graham Davies
  63. [SI-LIST] Re: Need advice on basic 6-layer stackup, Anders Frederiksen
  64. [SI-LIST] Question about hspice .probe command, Jihong Ren
  65. [SI-LIST] Re: Question about hspice .probe command, Craig Clewell
  66. [SI-LIST] si-list@freelists.org, Rui Pimenta
  67. [SI-LIST] Re: si-list@freelists.org, Viaene, Tim
  68. [SI-LIST] gyro, smitha.anand
  69. [SI-LIST] Re: gyro, Weinberg, Richard (Richard)
  70. [SI-LIST] DDR traces across different power plane, Pang Ning
  71. [SI-LIST] Question about the Equation in Handbook of Black Magic, Peter Zhu
  72. [SI-LIST] Re: DDR traces across different power plane, Pang Ning
  73. [SI-LIST] Re: Question about the Equation in Handbook of Black Magic, Peter Zhu
  74. [SI-LIST] [Fwd: SATA I eye diagram], giorgio ravesio
  75. [SI-LIST] PCB Leakage Currents, Christopher.Jakubiec
  76. [SI-LIST] Re: PCB Leakage Currents, Ed Sayre III
  77. [SI-LIST] Beginner for SI, kathiresan.kandasamy
  78. [SI-LIST] help, LBO
  79. [SI-LIST] Zdiff:100ohms?, Jayaprakash
  80. [SI-LIST] Intel SI Opportunity, e077636
  81. [SI-LIST] Mobile DDR DRAM, jjrree
  82. [SI-LIST] SwItChING FREQUENCY IN SPECCTRA QUEST, race
  83. [SI-LIST] What should I do RF package substrate design?, realbalm
  84. [SI-LIST] Crosstalk, Murali Mohan Repala (mrepala)
  85. [SI-LIST] bypass-caps: trade-off between capacitance and inductance, Sarah Bates
  86. [SI-LIST] Re: bypass-caps: trade-off between capacitance and inductance, zhangkun 29902
  87. [SI-LIST] Re: Need advice on basic 6-layer stackup - board warpage, Sol Tatlow
  88. [SI-LIST] Ferrite model, Kamran Azizi
  89. [SI-LIST] Re: Ferrite model, Ray Anderson
  90. [SI-LIST] Invite: Challenges, Opportunities and Solutions for Multi-Gigabit SerDes Seminar, Ken Reid
  91. [SI-LIST] Re: Invite: Challenges, Opportunities and Solutions for Multi-Gigabit SerDes Seminar, Muranyi, Arpad
  92. [SI-LIST] Re: Invite: Challenges, Opportunities and Solutions for Multi-Gigabit SerDes Seminar, steve weir
  93. [SI-LIST] Capacitance Matrix, Georgerian, Richard
  94. [SI-LIST] unsubscribe, Allen Tsai
  95. [SI-LIST] difference between two batches of main boards?, Abraham Peng
  96. [SI-LIST] diode connected between source & drain - why?, Roy M.
  97. [SI-LIST] Re: diode connected between source & drain - why?, Weinberg, Richard (Richard)
  98. [SI-LIST] Antw: diode connected between source & drain - why?, Robert Nowak
  99. [SI-LIST] Re: Capacitance Matrix, steve weir
  100. [SI-LIST] why use oblong pad?, jagaveer25
  101. [SI-LIST] Re: why use oblong pad?, Mike Greim
  102. [SI-LIST] FPGA career opportunity within RFID, George Carlson, CPC
  103. [SI-LIST] About Self coupling, Naren
  104. [SI-LIST] FastCap and FftCap Problem, Florian Helmut Müller
  105. [SI-LIST] unsubscribe, Chinh Tran
  106. [SI-LIST] Finding the impedance of a PCB trace, Graham Davies
  107. [SI-LIST] [Finding the impedance of a PCB trace, Graham Davies



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