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[SI-LIST] Re: Soldermask Impact Microstrip Impedance
- From: "ariazi" <ariazi@xxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 6 Apr 2005 09:48:27 -0700
Dear Peter Pang,
The soldermask coating on the top surface will increase the capacitance =
of
the
microstrip trace and hence decrease its characteristic impedance.
It is stated in an article by Dr. Eric Bogatin, "When Accuracy Counts"
(Published in Printed Circuit Design & Manufacture May 2003, P. 36) that
Zo decreases by approximately 1 Ohm/0.001 inch of soldermask thickness.
The trace width, dielectric substrate thickness and its Er are regarded =
to
possess first=20
order effect on Zo, whereas the effects of soldermask and trace =
thickness
are of second order.
Best Regards,
Abe Riazi
ServerWorks
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On
Behalf Of Pang Ning
Sent: Wednesday, April 06, 2005 6:21 AM
To: SI-LIST
Cc: Yang Wanguo(Tony); Tang Lan(Stella)
Subject: [SI-LIST] Soldermask Impact Microstrip Impedance
Dear experts,
I have a simple question for you about microstrip impedance. As you =
know,
many impedance calculation tools didn't consider soldermask influence =
when
counting microstrip impedance. Maybe the trace should be called as =
coated
microstrip or embeded microstrip. Because the dielectric constant of
soldermask is much bigger than air, and soldermask thickness is about
0.5mil~1mil, the real impedance on PCB will be smaller than the =
calculation
results from simulation tools. So would you please let me know how to =
deal
with this issue? Should the soldermask influence be taken into =
consideration
when calculating microstrip impedance? Thanks for your comments.
Thanks,
Best Regards,
Peter Pang
XGI Technology Inc.=20
------------------------------------------------------------------
=20
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