Date Index for si-list, 04-2003

[si-list] || [04-2003 Date Index] [04-2003 Thread Index]

[SI-LIST] regarding standards Fcc etc., - mbestha
[SI-LIST] XTK model for I2C bus - SI Eng
[SI-LIST] Re: XTK model for I2C bus - Guasti Giovanni
[SI-LIST] Re: XTK model for I2C bus - steve weir
[SI-LIST] Re: Skew and Jitter - Loyer, Jeff
[SI-LIST] Re: Skew and Jitter - Robert Haller
[SI-LIST] Re: Skew and Jitter - Todd Westerhoff
[SI-LIST] Re: Skew and Jitter - Jon Powell
[SI-LIST] Re: Skew and Jitter - Todd Westerhoff
[SI-LIST] Re: Skew and Jitter - Scott McMorrow
[SI-LIST] Signal Integrity Analysis Software - Mike Reynell
[SI-LIST] Re: Skew and Jitter - Clewell, Craig
[SI-LIST] Re: Signal Integrity Analysis Software - Rich Peyton
[SI-LIST] Re: Signal Integrity Analysis Software - Jon Powell
[SI-LIST] Re: Signal Integrity Analysis Software - Rich Peyton
[SI-LIST] Re: Skew and Jitter - Lynne Green
[SI-LIST] Re: Signal Integrity Analysis Software - Suresh Subramaniam
[SI-LIST] IBIS, si simulators, modeling and other sources of correlation error - Scott McMorrow
[SI-LIST] Re: IBIS, si simulators, modeling and other sources of correlation error - Jon Powell
[SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda - Hargin, Bill
[SI-LIST] Re: ePlanner(Scratchpad)/XTK from Innoveda - k EPD
[SI-LIST] Re: Skew and Jitter - Jonathan Dowling
[SI-LIST] Re: IBIS, si simulators, modeling and other sources of correlation error - e.sweetman
[SI-LIST] Routing of 12 GHz diff pairs - buck
[SI-LIST] Re: Routing of 12 GHz diff pairs - Juergen Hannappel
[SI-LIST] Re: Routing of 12 GHz diff pairs - Guasti Giovanni
[SI-LIST] Re: Routing of 12 GHz diff pairs - Erik Jacobs
[SI-LIST] crosstalk-FastCap - manthos labropoulos
[SI-LIST] IEEE CPMT Society Phoenix Chapter - April 15 meeting announcement - Sam Karikalan
[SI-LIST] Re: Routing of 12 GHz diff pairs - Scott McMorrow
[SI-LIST] Re: IEEE CPMT Society Phoenix Chapter - April 15 meeting announcement - Ed Beckett
[SI-LIST] Re: Routing of 12 GHz diff pairs - Alex Horvath
[SI-LIST] Re: Routing of 12 GHz diff pairs - Jean Audet
[SI-LIST] Re: Routing of 12 GHz diff pairs - Jon Powell
[SI-LIST] Lookig for Signal Integrity Position - SRCoe
[SI-LIST] Re: IBIS, si simulators, modeling and other sources of correlation error - Beal, Weston
[SI-LIST] Re: Routing of 12 GHz diff pairs - e.sweetman
[SI-LIST] Re: Routing of 12 GHz diff pairs - Dorin
[SI-LIST] Re: IBIS, si simulators, modeling and other sourcesof correlation error - Scott McMorrow
[SI-LIST] Re: IBIS, si simulators, modeling and other sourcesof correlation error - Scott McMorrow
[SI-LIST] Re: Routing of 12 GHz diff pairs - Fabrizio Zanella
[SI-LIST] Re: Routing of 12 GHz diff pairs - Chris Cheng
[SI-LIST] crosstalk-FastCap - manthos labropoulos
[SI-LIST] Coupled connector model - David Fogel
[SI-LIST] Analyzing noise in chip packages - Doug Smith
[SI-LIST] What is Latium Error?? - Binosh Balachandra
[SI-LIST] Re: Coupled connector model - Corey Kimble
[SI-LIST] Re: What is Latium Error?? - Ray Anderson
[SI-LIST] Re: What is Latium Error?? - Ken Cantrell
[SI-LIST] Re: What is Latium Error?? - Scott McMorrow
[SI-LIST] Re: Coupled connector model - Robert Haller
[SI-LIST] Re: Coupled connector model - Scott McMorrow
[SI-LIST] Re: What is Latium Error?? - Muranyi, Arpad
[SI-LIST] Re: What is Latium Error?? - Lori Lesnick
[SI-LIST] loss tangent calculation - atifshamim khan
[SI-LIST] Re: loss tangent calculation - Jian X. Zheng
[SI-LIST] What Latium is - Lori Lesnick
[SI-LIST] Re: What Latium is - Ingraham, Andrew
[SI-LIST] Re: What Latium is - Lori Lesnick
[SI-LIST] Re: What Latium is - Todd Westerhoff
[SI-LIST] Re: What Latium is - Bill Reams
[SI-LIST] Re: What Latium is - David Fogel
[SI-LIST] Re: Loss tangent calculation - Tabatchnick, Justin
[SI-LIST] Re: What Latium is - Brian Schieck
[SI-LIST] Re: Loss tangent calculation - Robert Plant
[SI-LIST] Re: Loss tangent calculation - Tabatchnick, Justin
[SI-LIST] Re: Loss tangent calculation - andrew . c . byers
[SI-LIST] Re: Loss tangent calculation - Jian X. Zheng
[SI-LIST] test,I am a new member - maxiu
[SI-LIST] Re: Loss tangent calculation - Robert Plant
[SI-LIST] Language conventions - Doug Brooks
[SI-LIST] Re: Language conventions - Loyer, Jeff
[SI-LIST] Re: Language conventions - Jackson, T L
[SI-LIST] Re: Language conventions - Doug Winterberg
[SI-LIST] Re: Language conventions - Ross_Amans
[SI-LIST] Re: Language conventions - Ingraham, Andrew
[SI-LIST] Re: Language conventions - Chris Peake
[SI-LIST] Re: Language conventions - Steve Horne
[SI-LIST] Re: Language conventions - Knighten, Jim L
[SI-LIST] Re: Language conventions - John Thomas
[SI-LIST] Re: Language conventions - Abhijit Mahajan
[SI-LIST] Re: Language conventions - Ingraham, Andrew
[SI-LIST] Re: Language conventions - Larry Barnes
[SI-LIST] Re: Language conventions - Ray Anderson
[SI-LIST] Re: Language conventions - Abhijit Mahajan
[SI-LIST] Re: Language conventions - Ivor Bowden
[SI-LIST] Re: Language conventions - Ross_Amans
[SI-LIST] Re: Language conventions - Knighten, Jim L
[SI-LIST] Re: Language conventions - Peter Arnold
[SI-LIST] R-T-F-M Re: Language conventions - Feldman, Richard
[SI-LIST] Re: R-T-F-M Re: Language conventions - Muranyi, Arpad
[SI-LIST] Re: R-T-F-M Re: Language conventions - Jon Powell
[SI-LIST] worst-case / best-case - Yoni Tzafrir
[SI-LIST] Re: worst-case / best-case - Mike Mayer
[SI-LIST] digital vector - Yoni Tzafrir
[SI-LIST] digital vector - Yoni Tzafrir
[SI-LIST] Re: digital vector - Ingraham, Andrew
[SI-LIST] Re: digital vector - Scott McMorrow
[SI-LIST] Re: digital vector - Jon Powell
[SI-LIST] Maxwell matrixes in Hspice - manthos labropoulos
[SI-LIST] PRBS generation for hspice - timoceous
[SI-LIST] Re: [SI-LIST]Language conventions - Henrik G. Madsen
[SI-LIST] measuring active-to-float time for PCI o/p buffer - adeel . ahmad
[SI-LIST] Re: Language conventions - Bill Reams
[SI-LIST] Material on SI in ASIC - Shripadaraj Annigeri
[SI-LIST] Re: Material on SI in ASIC - John Barnes
[SI-LIST] Re: stitched via shielding - Jim G Roberts
[SI-LIST] IBIS Modeling Tools - Paradis, Daniel
[SI-LIST] Signal Integrity Manager Position at AMD -- Austin, TX - Jonathan Dowling
[SI-LIST] Re: measuring active-to-float time for PCI o/p buffer - Sandy Taylor
[SI-LIST] Cat 5 cable properties... - Cesar Coba
[SI-LIST] question concerning socket for SDRAM module - mechanical problem? - Jan Vercammen
[SI-LIST] different Vmeas for Rising/Falling - SI Eng
[SI-LIST] Re: different Vmeas for Rising/Falling - Jon Powell
[SI-LIST] Re: different Vmeas for Rising/Falling - Mirmak, Michael
[SI-LIST] Re: question concerning socket for SDRAM module - mechanical problem? - Matthew Humphreys
[SI-LIST] Re: different Vmeas for Rising/Falling - Moran, Brian P
[SI-LIST] Re: different Vmeas for Rising/Falling - Moran, Brian P
[SI-LIST] Re: different Vmeas for Rising/Falling - Moran, Brian P
[SI-LIST] Standards - Rich Peyton
[SI-LIST] Re: question concerning socket for SDRAM module - mechanical problem? - John Thomas
[SI-LIST] Question Concerning End Launch SMA connector. - Gustavo Blando
[SI-LIST] Re: Question Concerning End Launch SMA connector. - Tabatchnick, Justin
[SI-LIST] Re: Question Concerning End Launch SMA connector. - Tabatchnick, Justin
[SI-LIST] Fw: Question Concerning End Launch SMA connector. - e.sweetman
[SI-LIST] Re: Question Concerning End Launch SMA connector. - Gary Otonari
[SI-LIST] Buffer Delay - Gil Gafni
[SI-LIST] serial loop-back causing clock error - Hong Shi
[SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX - Priyawrat Dewasthalee
[SI-LIST] Difference in simulations results between Hspice and Pspice-ORCAD. - Parthasarathy Sampath
[SI-LIST] Re: Difference in simulations results between Hspice and Pspice-ORCAD. - Raymond . Leung
[SI-LIST] Re: serial loop-back causing clock error - Raymond . Leung
[SI-LIST] Re: Signal Integrity Manager Position at zzz - Al Davis
[SI-LIST] PECL vs LVDS - hariharan
[SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX - Peterson, James F (FL51)
[SI-LIST] Re: Question Concerning End Launch SMA connector. - Swanson, Dan
[SI-LIST] Test - Marowsky, Rich
[SI-LIST] Re: Coupled connector model - Gangyao Xiao
[SI-LIST] TRST signal of JTAG I/F - Nico Fleurinck
[SI-LIST] Converting S-parameter to Inductance and Capacitance - H H Goh
[SI-LIST] Re: TRST signal of JTAG I/F - CJ Clark
[SI-LIST] Radiating Ceramic Bulk Capacitors - Paradis, Daniel
[SI-LIST] Re: question concerning socket for SDRAM module - mechanical problem? - Brown, Mike (AUS)
[SI-LIST] Re: TRST signal of JTAG I/F - Ingraham, Andrew
[SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX - Ken Cantrell
[SI-LIST] Re: Converting S-parameter to Inductance and Capacitance - Hassan O. Ali
[SI-LIST] Re: Signal Integrity Manager Position at AMD -- Austin, TX - Jon Powell
[SI-LIST] Re: PECL vs LVDS - Ingraham, Andrew
[SI-LIST] Re: Converting S-parameter to Inductance and Capacitance - Hassan O. Ali
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Jon Powell
[SI-LIST] Re: Buffer Delay - Jon Powell
[SI-LIST] Re: PECL vs LVDS - Jim G Roberts
[SI-LIST] help - Marowsky, Rich
[SI-LIST] Re: TRST signal of JTAG I/F - Arul Jothi
[SI-LIST] Re: help - Jon Powell
[SI-LIST] unset [listname] vacation - Marowsky, Rich
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Istvan Novak - Board Design Technology
[SI-LIST] a clocking scheme question - Peterson, James F (FL51)
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - John Barnes
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Paradis, Daniel
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Larry Smith
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Paradis, Daniel
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Istvan Novak - Board Design Technology
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Paradis, Daniel
[SI-LIST] Creating Cable Models in SPECCTRAquest - Geistlinger, Marlow K
[SI-LIST] Re: a clocking scheme question - MikonCons
[SI-LIST] wats ferrite affection - zhou lin
[SI-LIST] Re: Buffer Delay - Jack Stone
[SI-LIST] Re: Buffer Delay - Raymond . Leung
[SI-LIST] Re: Buffer Delay - Parthasarathy Sampath
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Bart Bouma
[SI-LIST] Re: a clocking scheme question - Jim G Roberts
[SI-LIST] Converting S-para to L,C --Si list - Eoin Mc Gibney
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Paradis, Daniel
[SI-LIST] Re: Radiating Ceramic Bulk Capacitors - Steve Lund
[SI-LIST] Twist ratio in a Cat 5 cable - Cesar Coba
[SI-LIST] IS DEPT TESTING EMAIL Filtering - Marowsky, Rich
[SI-LIST] SPICE model - Hong Shi
[SI-LIST] Backplane 'overaly' question - Bill Dempsey
[SI-LIST] LVDS Termination - Siders, Kenneth W
[SI-LIST] Re: SPICE model - Abhay Apte
[SI-LIST] Re: Converting S-parameter to Inductance and Capacitance - Ben Chia
[SI-LIST] Re: LVDS Termination - Mike Brown
[SI-LIST] Re: LVDS Termination - Tabatchnick, Justin
[SI-LIST] Series Termination Resistance - SUDARSHAN
[SI-LIST] Re: LVDS Termination - Mike Brown
[SI-LIST] Re: SPICE model - Alicia Corrales Chanca
[SI-LIST] FW: TRST signal of JTAG I/F - Nico Fleurinck
[SI-LIST] Re: TRST signal of JTAG I/F - Dimiter Popoff
[SI-LIST] Re: LVDS Termination - Boris Yost
[SI-LIST] Re: LVDS Termination - Jim G Roberts
[SI-LIST] Re: Series Termination Resistance - Jim G Roberts
[SI-LIST] Re: Series Termination Resistance - David Schaefer
[SI-LIST] Re: LVDS Termination - Grasso, Charles
[SI-LIST] The return of nickel! - Boris Yost
[SI-LIST] Re: Buffer Delay - Ingraham, Andrew
[SI-LIST] Re: The return of nickel! - jeff_latourrette
[SI-LIST] Re: LVDS Termination - Mike Brown
[SI-LIST] Re: The return of nickel! - istvan novak
[SI-LIST] Re: The return of nickel! - Boris Yost
[SI-LIST] Immersion gold - Martin Euredjian
[SI-LIST] Re: Immersion gold - Jon Keeble
[SI-LIST] Question: Circuit representation of partially filled soleniod withinductors. - Abdulrahman Rafiq
[SI-LIST] Re: Immersion gold - Lee Ritchey
[SI-LIST] SMII interface imped design - qzheng
[SI-LIST] SPI03 ADVANCE REGISTRATION DEADLINE AND PROGRAM - Carla Giachino
[SI-LIST] search for clock oscillator - Nico Fleurinck
[SI-LIST] Re: search for clock oscillator - Clewell, Craig
[SI-LIST] Power distribution - Tom
[SI-LIST] Re: Power distribution - Jim G Roberts
[SI-LIST] Re: Power distribution - Robert Haller
[SI-LIST] search for clock oscillator - Jim G Roberts
[SI-LIST] Re: Immersion gold - Martin Euredjian
[SI-LIST] Re: SPI03 ADVANCE REGISTRATION DEADLINE AND PROGRAM - Drew
[SI-LIST] Spiral Inductor - Vijay Varadarajan
[SI-LIST] Re: LVDS Termination - Dr. Howard Johnson
[SI-LIST] Re: Immersion gold - Moran, Brian P
[SI-LIST] TV tuner chips - Sankar karuppannan
[SI-LIST] Buffering 125MHz GMII signals - Samir Gundawar
[SI-LIST] Re: Buffering 125MHz GMII signals - Sankar karuppannan
[SI-LIST] Re: Immersion gold - szimmer
[SI-LIST] Re: Immersion gold - Lee Ritchey
[SI-LIST] DIMM power consumption - Lucas Bossetti
[SI-LIST] Re: Buffering 125MHz GMII signals - Vinu Arumugham
[SI-LIST] Re: Spiral Inductor - D G
[SI-LIST] Re: Spiral Inductor - Vijay Varadarajan
[SI-LIST] Re: Spiral Inductor - atifshamim khan
[SI-LIST] pin type definition for Mentor Expedition - Kupper, Ingo
[SI-LIST] Does ferrite rod affect inductance ? - zhou lin
[SI-LIST] high speed digital design decoupling question - Nico Fleurinck
[SI-LIST] Test Message - Ahmad Fallah
[SI-LIST] Re: Buffering 125MHz GMII signals - Henrik G. Madsen
[SI-LIST] Re: Spiral Inductor - Swanson, Dan
[SI-LIST] coax to PCB transition - return loss - Perry Qu
[SI-LIST] Re: coax to PCB transition - return loss - Guasti Giovanni
[SI-LIST] Re: Does ferrite rod affect inductance ? - Vadim Heyfitch
[SI-LIST] New Software - Juan Manuel
[SI-LIST] New Software Question - webhugo-gcn
[SI-LIST] Measuring Crosstalk - Aaron Helleman
[SI-LIST] Help: how to create IBIS model for a chip which contains two dies - Lu
[SI-LIST] Re: Spiral Inductor - Vijay Varadarajan
[SI-LIST] Seeking SI opportunities - win bery
[SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies - Crain, Dan S
[SI-LIST] Transceiver - Lim, Chia Nian
[SI-LIST] IBIS Model VT Curve Length - Moran, Brian P
[SI-LIST] What's difference between 3.5mm and SMA? - Moore Mo (Mo Daochun)
[SI-LIST] Re: What's difference between 3.5mm and SMA? - hansm
[SI-LIST] Re: What's difference between 3.5mm and SMA? - Tom Dagostino
[SI-LIST] right pulse shape test way - Gao Xiaoting
[SI-LIST] AD bus - Nimish Aggarwal
[SI-LIST] diff-pair - Nimish Aggarwal
[SI-LIST] Re: diff-pair - Parthasarathy Sampath
[SI-LIST] via resistance - Paolo Peruzzi
[SI-LIST] Re: What's difference between 3.5mm and SMA? - Fasig, Jonathan L.
[SI-LIST] SPI4.2 over cable - Siva kumar
[SI-LIST] Re: Measuring Crosstalk - Robert Haller
[SI-LIST] Re: IBIS Model VT Curve Length - Todd Westerhoff
[SI-LIST] EPEP Books - Sainath Nimmagadda
[SI-LIST] Re: Help: how to create IBIS model for a chip which containstwo dies - Lu
[SI-LIST] Re: What's difference between 3.5mm and SMA? - e.sweetman
[SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies - Crain, Dan S
[SI-LIST] Signal Integrity Engineer Seeking Position - e.sweetman
[SI-LIST] Re: Measuring Crosstalk - Jack Stone
[SI-LIST] Re: Measuring Crosstalk - Crain, Dan S
[SI-LIST] Re: IBIS Model VT Curve Length - Jon Powell
[SI-LIST] Jobs Opening - Patrick Lam
[SI-LIST] Jobs Opening - Patrick Lam
[SI-LIST] Re: IBIS Model VT Curve Length - Donnelly, Mike
[SI-LIST] Re: IBIS Model VT Curve Length - Scott McMorrow
[SI-LIST] RS232 transmit and receive frequency - Youssef Khalife
[SI-LIST] [Q] Usual trace length for 64bit-wide bus using 250Mbps HSTL - cts
[SI-LIST] PEN Leslie Margaret Mary L/Snr Assoc Engr/STATS/ST Group is out of theoffice. - penlmml
[SI-LIST] HSPICE 2003.03 W-element concern - Ed Sayre III
[SI-LIST] Electrical Modeling Consultants (Bay Area) - Bob McCreight
[SI-LIST] Re: [Fwd: coax to PCB transition - return loss] - Loyer, Jeff
[SI-LIST] Re: [Fwd: coax to PCB transition - return loss] - Scott McMorrow
[SI-LIST] Re: IBIS Model VT Curve Length - Muranyi, Arpad
[SI-LIST] Re: IBIS Model VT Curve Length - Vadim Heyfitch
[SI-LIST] Re: IBIS Model VT Curve Length - Muranyi, Arpad
[SI-LIST] Re: IBIS Model VT Curve Length - Vadim Heyfitch
[SI-LIST] Re: IBIS Model VT Curve Length - Jon Powell
[SI-LIST] test - please ignore - Dimiter Popoff
[SI-LIST] Re: What's difference between 3.5mm and SMA? - D G
[SI-LIST] Re: [Fwd: coax to PCB transition - return loss] - bpanos
[SI-LIST] Re: [Fwd: coax to PCB transition - return loss] - Scott McMorrow
[SI-LIST] Re: Electrical Modeling Consultants (Bay Area) - Bob McCreight
[SI-LIST] Common Mode Return Loss Measurements - Ray Anderson
[SI-LIST] EMI--bare board vs. case - Boris Yost
[SI-LIST] Re: Common Mode Return Loss Measurements - Gary Otonari
[SI-LIST] Re: Common Mode Return Loss Measurements - Loyer, Jeff
[SI-LIST] Re: Common Mode Return Loss Measurements - Loyer, Jeff
[SI-LIST] Center of Mass of Transistors. - Parthasarathy Sampath
[SI-LIST] Re: EMI--bare board vs. case - Vishram Pandit
[SI-LIST] Re: EMI--bare board vs. case - Val Mandrusov
[SI-LIST] Validation of spiral inductors - Gurumurthy, Radhika
[SI-LIST] How to terminate the bi-directional buses? - C.Y. Cheng
[SI-LIST] Re: How to terminate the bi-directional buses? - Hans Klos
[SI-LIST] Re: Common Mode Return Loss Measurements - Charles Hill
[SI-LIST] Re: HSPICE 2003.03 W-element concern - Michael_Greim
[SI-LIST] Re: [Fwd: coax to PCB transition - return loss] - Perry Qu
[SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office. - Steve . Wood
[SI-LIST] Re: [Fwd: coax to PCB transition - return loss] - Loyer, Jeff
[SI-LIST] Re: Center of Mass of Transistors. - Tom Biggs
[SI-LIST] Re: Center of Mass of Transistors. - Tom Biggs
[SI-LIST] Re: Center of Mass of Transistors. - Tom Biggs
[SI-LIST] Re: [Fwd: coax to PCB transition - return loss] - Perry Qu
[SI-LIST] Measuring Power/Gnd - Gary Otonari
[SI-LIST] Re: [Fwd: coax to PCB transition - return loss] - Loyer, Jeff
[SI-LIST] Re: Common Mode Return Loss Measurements - Dima Smolyansky
[SI-LIST] N-port model limitations in simulators - Ray Anderson
[SI-LIST] Re: N-port model limitations in simulators - Muranyi, Arpad
[SI-LIST] Re: N-port model limitations in simulators - Charles Hill
[SI-LIST] Re: N-port model limitations in simulators - Zhangkun
[SI-LIST] Re: N-port model limitations in simulators - Ege Engin
[SI-LIST] spacing between via - hariharan
[SI-LIST] VNA Calibration for COAX Testing - Moeller, Merrick
[SI-LIST] Re: N-port model limitations in simulators - Jian X. Zheng
[SI-LIST] series term + fanout = noise? - Boris Yost
[SI-LIST] Re: series term + fanout = noise? - Bill Dempsey
[SI-LIST] Re: VNA Calibration for COAX Testing - Moeller, Merrick
[SI-LIST] Re: VNA Calibration for COAX Testing - D G
[SI-LIST] Re: series term + fanout = noise? - Ravinder Ajmani
[SI-LIST] Re: N-port model limitations in simulators - JuYoung Lee
[SI-LIST] Help on Jtag Emulator connection for Debugging TI DSP - SUDARSHAN
[SI-LIST] Re: digital vector - Yoni Tzafrir
[SI-LIST] Simulation error - Alicia Corrales Chanca
[SI-LIST] Re: Help: how to create IBIS model for a chip which containstwo dies - Lu
[SI-LIST] Re: Help: how to create IBIS model for a chip which contains two dies - Jon Powell
[SI-LIST] Re: Simulation error - Jon Powell
[SI-LIST] Re: digital vector - Jon Powell
[SI-LIST] Re: Simulation error - jeff_latourrette
[SI-LIST] Looking for Spectrum Analyzer info - Gary Thompson
[SI-LIST] RS232 and RS422 - Moustapha Abdi Hassan
[SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office. - Steve . Wood
[SI-LIST] Where can get RGB signal's spec? - Jack W.C. Lin
[SI-LIST] test - Moses Chan
[SI-LIST] regarding noise in LVDS - jan man
[SI-LIST] Re: N-port model limitations in simulators - Muranyi, Arpad
[SI-LIST] FW: RS232 and RS422 - Moustapha Abdi Hassan
[SI-LIST] Re: N-port model limitations in simulators - Ray Anderson
[SI-LIST] Re: N-port model limitations in simulators - Larry Smith
[SI-LIST] Re: N-port model limitations in simulators - Charles Hill
[SI-LIST] Re: N-port model limitations in simulators - Zhangkun
[SI-LIST] Re: N-port model limitations in simulators - Larry Smith
[SI-LIST] transformer model - zanglinyuan
[SI-LIST] Re: N-port model limitations in simulators - Joel R. Phillips
[SI-LIST] Re: transformer model - npischl
[SI-LIST] Test Loading Issues on Quad XTK - lting168
[SI-LIST] Re: Where can get RGB signal's spec? - Stuart Benner
[SI-LIST] Re: Test Loading Issues on Quad XTK - Jon Powell
[SI-LIST] Re: N-port model limitations in simulators - Raj Raghuram
[SI-LIST] Re: N-port model limitations in simulators - Steve Corey
[SI-LIST] Re: N-port model limitations in simulators - Steve Corey
[SI-LIST] Re: N-port model limitations in simulators - Larry Smith
[SI-LIST] Re: N-port model limitations in simulators - Ray Anderson
[SI-LIST] Re: N-port model limitations in simulators - Larry Smith
[SI-LIST] Joined - VIKAS SHUKLA
[SI-LIST] Joined - VIKAS SHUKLA
[SI-LIST] Re: Test Loading Issues on Quad XTK - Abe Riazi
[SI-LIST] Gold plating reference(s) - Fasig, Jonathan L.
[SI-LIST] Shape factors for sheet resistance based estimations - Jerry Martinson
[SI-LIST] DDR SDRAM Help Request - Paul Levin
[SI-LIST] Re: DDR SDRAM Help Request - Mangipudi, Prasad
[SI-LIST] Re: DDR SDRAM Hints - Paul Levin
[SI-LIST] Re: Test Loading Issues on Quad XTK - lting168
[SI-LIST] Re: Shape factors for sheet resistance based estimations - Hal Murray
[SI-LIST] Re: Test Loading Issues on Quad XTK - David Fogel
[SI-LIST] Re: Test Loading Issues on Quad XTK - Jon Powell
[SI-LIST] Re: N-port model limitations in simulators - Yu Liu
[SI-LIST] Differential Signal at driver and intermediate points in xtk - VIKAS SHUKLA
[SI-LIST] Embedded capacitors - Steve Rogers
[SI-LIST] Embedded inductors - Steve Rogers
[SI-LIST] Re: Differential Signal at driver and intermediate points in xtk - Jon Powell
[SI-LIST] Re: Differential Signal at driver and intermediate points in xtk - Jon Powell
[SI-LIST] Re: Differential Signal at driver andintermediatepoints in xtk - Abe Riazi
[SI-LIST] Re: SDRAM bus termination - San Miguel, Shane
[SI-LIST] Re: SDRAM bus termination - Mehrdad Salami
[SI-LIST] Re: N-port model limitations in simulators - Larry Smith
[SI-LIST] RMCEMC May Bonus Meeting - Grasso, Charles
[SI-LIST] Re: N-port model limitations in simulators - Yu Liu