FreeLists / si-list / [SI-LIST] Re: Source-Synchronous Interface

["Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>]

> 1. How does one determine min and max lengths for ss interface? Is it
> based on
> loading and signal quality only?

Partly.

Also, the longer the traces, the greater the mismatch in their delays.

Also, many source-synchronous interfaces eventually need to
synchronize with an outer common clock domain, so there would be
some maximum delay across the source-synchronous interface that can
be tolerated.

> 2. What are the various factors taken into account for tolerance(say,
> within a
> group) determination, other than PCB skew?

On-chip clock skew.

Delay skew of the output buffers.

Simultaneous switching delay adders.

Package skew.

Crosstalk in the IC packages.

PCB crosstalk.

Input thresholds.

Edge rate degradation.

etc.


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