FreeLists / si-list / [SI-LIST] PCI Buffer Slew Rate

["Gregory R Edlund" <gedlund@xxxxxxxxxx>]

Gil,

This seems really strange to me.  I've seen 100-200 ps of SSO push-out on a
well designed driver of the kind you are describing.  This corresponds to
rail collapse of ~500 mV on a 3.3V rail.  I would expect on-chip noise to
be less than half this and the corresponding delay hit to be less as well.
How are you modeling the core power distribution?  Is there anything usual
about the pre-drive stage of your driver?

Greg Edlund
Advisory Engineer
Electronic Packaging Integration
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@xxxxxxxxxx


From: "Gil Gafni" <ggafni@xxxxxxxxxxxxxxxxxxxxx>
Subject: [SI-LIST] PCI Buffer Slew Rate
Date: Wed, 10 Apr 2002 12:20:55 -0700

Hello Experts,

As part of an SSO analysis that we are conducting, we noticed an odd
behavior of the PCI buffer -
1.           It looks like it is influenced by the noise on the core Vdd
(logic side of it) and NOT to the IO Vdd.
2.           The sensitivity to Vdd core changes is very high; any added
100mV of noise can add 1nSec to the pushout.

The bottom line is that with a moderate noise on Vdd of 375 mV we have
1nS of push out, and find it very hard to pass (no or negative margins)
Any recommendations?

Regards,

Gil Gafni




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