FreeLists / si-list / [SI-LIST] Re: SSO pushout

[adeel.ahmad@xxxxxx]

hello,

how i would relate the gnd bounce to delays is this-

consider a CMOS driver stage with an NMOS transistor that pulls down the
pad output to low.
                        -------PAD
                        |
                        |
                      NMOS
                        |
                        |<<internal GND
                     INDUCTOR   
                        |
                    GROUND PIN                  


in the above figure, with PAD initially at some VCC,nmos is switched on.
this causes a bounce at the internal GND connected to nmos terminal due
to the presence of inductor. 
the output fall delay depends on how fast the current from load is
allowed to sink into the GROUND. but with the bounce at internal GND, the
potential across the terminals of the NMOS(Source and Drain) is reduced
that means the Vds of nmos is reduced, which reduces the current sink
capability of the nmos.(the current through nmos is always dependent on
Vds though more when nmos is in non-saturated region).

hope this example relates the delay with the ground bounce.


ADEEL AHMAD
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