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[SI-LIST] Re: SSO pushout

  • From: "Ed Priest" <epriest@xxxxxxxxxxxxxxxxxxx>
  • To: <amahajan@xxxxxxxxxxxx>, <linwee70@xxxxxxxxx>
  • Date: Wed, 10 Apr 2002 14:32:49 -0700
Two things:

Capacitance is due to the geometry and not the voltage. Capacitance of a
trace is independent of voltage (charge stored is a function of
voltage). A 3pf cap is a 3pf cap with 2v or 5v.=20


SSO pushout is a Coulomb starvation problem with the driver and is not a
function of the interconnect. When a "bunch" of drivers switch and if
there is not enough local charge storage the voltage will drop and the
transistors will slow down.=20

Ed
-----Original Message-----
From: Abhijit Mahajan [mailto:amahajan@xxxxxxxxxxxx]=20
Sent: Wednesday, April 10, 2002 1:54 PM
To: linwee70@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: SSO pushout


One way to explain this is as follows:

The mutual capacitance between the lines doubles when the neighbouring
outputs switch
in a direction opposite to the victim line.  This means that the signal
on the victim line now
takes longer to rise due to the added capacitance hence increasing the
delay.





Lin Wee wrote:

> Hello:
>
> I was reading some SI paper that says:
>
> " SSO pushout is a result of multiple drivers
> switching simultaneously. It impacts signal integrity
> through adding extra delay to the propagating signal"
>
> I understand that we'll have more current in the
> return path due to simultaneous switching that may
> cause ground/plane bounce, but couldn't relate that to
> delay.
>
> Can someone explain this  delay, as the text doesn't
> explain that ?
>
> Thanks;
> -Lin
>
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