[SI-LIST] Re: AW: Re: PCB via simulations

["Gary Haussmann" <gary.haussmann@xxxxxxxxxxxxxxx>]

Thomas and Dan,

The default boundary condition for the tool "LC" used in these simulations
is a first-order Mur absorbing boundary.  I've looked at the model file and
this appears to be the boundary that was used in the simulations.  The
first-order Mur boundary is typically intended for outgoing space waves, so
for this guided wave simulation it may not be ideal.  However, these are
definately not "conducting wall" boundaries.


I've simulated the model with a better absorber--the perfectly matched layer
(PML) and see no real difference compared to the original results.
Simulating a third time with electrically conducting boundaries totally
distorts the reflected and transmitted waveforms, however.  So I think the
original boundaries--Mur absorbing boundaries--work reasonably well for this
problem, even if they aren't perfect.


In any case, the original via simulation has a 4 mil spacing between power
and ground planes along with a 10ps rise time.  I would think that the bulk
of the return current is composed mainly of displacement current between the
two planes, so decoupling caps or "return along the boundaries" have little
effect.  If you were looking at much slower pulses like 1ns, or moved the
planes farther apart, then the simulation boundaries would have a noticable
effect (assuming they are not conducting walls).  Also, decoupling
capacitors wouldn't matter much at the 30GHz+ frequencies in the original
simulation, but for slower pulses you will need some connection between the
two planes.  As Dan said, it's a matter of the frequencies used.


Gary




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Thomas Beneken
Sent: Monday, April 01, 2002 7:36 AM
To: DSWANSON@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] AW: Re: PCB via simulations



Hi Dan,

You are perfectly right:

a) The coupling capacitor between power plane and ground plane near the v=
ia
is missing.
b) The perfectly conducting boundary box must be dragged away far enough
from the ends of the TL not to influence the ports.
c) Free space approximation for the boundary is even better. (but the
Algorithm is more complicated and calculation time increases)

Thank You

Thomas


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• References:
  • [SI-LIST] AW: Re: PCB via simulations
    • From: Thomas Beneken

Other related posts:

[SI-LIST] AW: Re: PCB via simulations

[SI-LIST] AW: Re: PCB via simulations

[SI-LIST] Re: AW: Re: PCB via simulations