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[SI-LIST] Re: Raltion between tr to tpd for buffer
- From: "Nash, Timothy J" <timothy.j.nash@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 28 Mar 2008 09:19:31 -0600
To that end, some chip vendors even go as far as to offer IO compliant
to electrical standards such as PCI, which include constraints on edge
rates, but still fail to control them.
Tim
______________________________________
Timothy J. Nash, P.E.
Staff Electrical Engineer
Lockheed Martin Coherent Technologies
135 S. Taylor Ave.
Louisville, CO 80027-3025
Phone: (303) 729-5497
Fax: (303) 604-2500
Email: timothy.j.nash@xxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Peterson, James F (EHCOE)
Sent: Friday, March 28, 2008 7:42 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Raltion between tr to tpd for buffer
I will give you my opinion on this (since it is a button of mine).
Many times the chip designer is concerned about Tco (aka Tdo) and the
technology of the io buffer (SSTL, LVCMOS, etc.), but <I believe> many
of them give absolutely no consideration to the dv/dt (or rise time) of
the buffer.
The result, I see 64 bit buses with a 5 ns Tco and 200ps rise time. So,
even though this bus is obviously designed as a slower interface (Tco of
5ns), it has signals toggling at a gigabit rate. Thus, the poor board
guy ends up having to add 64 termination resistors onto the board. (I
believe this example's rise time should have been around 1ns.)
Several chip vendors are guilty of this. I will not identify them here,
but I will name some companies that do consider this and do an excellent
job of scaling the rise times according to the IO performance. Companies
that I feel do a great job of this are Xilinx, Altera, IBM, hmmm...I'm
sure there are others.
Thanks for letting me vent.
Regards,
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Narayane Manish Shivdas, TLS,Chennai
Sent: Friday, March 28, 2008 8:36 AM
To: Gil Simsic (SBC); si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Raltion between tr to tpd for buffer
So what should be rule of thumb? Plz reply.
Thanks & regards,
Manish
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Gil Simsic (SBC)
Sent: Thursday, March 06, 2008 9:44 PM
To: Narayane Manish Shivdas, TLS,Chennai; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Raltion between tr to tpd for buffer
Greetings Manish
There is indeed a relationship between the Tpd and the Tr, but in some
IO=3D20
standards, or IO cells it might be minute and negligible.
Your question is very generic and since you did not point out a specific
standard or technology I will give you my generic analogy -
The Tr defines the change of voltage per time of the input signal to an
IO=3D20
cell. As all IO cells build of transistors, either CMOS or TTL, they are
bound to the basic rules of - once you pass a specific threshold, you
bias=3D20
the junction in a way that it will either be active or saturated (I
simplify=3D20
it of course)
So when the input to an IO cell changes from low to high (i.e. Tr)
the=3D20
various transistors' biasing will change.
So simply putting it, the rate of change (Tr) will dictate how fast they
will move from saturation to active for instance, and through the linear
stage of the Tr there will be a linear influence on those transistors.
Hope it helps
Gil
----- Original Message -----=3D20
From: "Narayane Manish Shivdas, TLS,Chennai" <manishsn@xxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Thursday, March 06, 2008 7:55 AM
Subject: [SI-LIST] Raltion between tr to tpd for buffer
> Hello All,
>
> I am doing signal integrity analysis. Can I come to know
> the should be relation between the maximum and min propagation delay
of
> the input signal to the buffer propagation delay.
>
>
>
> Thanks & Regards,
>
> Manish
>
>
>
>
>
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Other related posts:[SI-LIST] Raltion between tr to tpd for buffer [SI-LIST] Re: Raltion between tr to tpd for buffer [SI-LIST] Re: Raltion between tr to tpd for buffer [SI-LIST] Re: Raltion between tr to tpd for buffer [SI-LIST] Re: Raltion between tr to tpd for buffer
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